Multi-core developments from the FP7 parMERASA project
This month sees the end of the three year FP7 parMERASA project – "Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability". The project has looked at the challenges of parallelized execution for mixed criticality in the domains of Avionics (Honeywell), Automotive (Denso) and construction machinery (Bauer), with academic partners from University of Augsburg, Barcelona Supercomputing Center, Université Paul Sabatier and Technical University of Dortmund.
In this blog I will summarize Rapita’s contributions to multi-core verification from parMERASA, as presented at the public dissemination event in Barcelona last week. Our full slides can be found at http://www.parmerasa.eu/files/dissemination_event/verification.pdf
All Rapita’s developments are related to two of the big challenges for multi-core embedded software and managing shared resources:
- Mutual exclusion of shared resources which is required for safety and security.
- Synchronisation between cores using barriers
Code Coverage for Multi-core
To support code coverage for multi-core we have extended the coverage results visualization with support to show which core a particular statement of code was executed on. Also, we have full coverage reports for each core.
Most importantly, we have extended our RapiCover code coverage tool to assess coverage to and from barriers. This first means ensuring that all barriers in your software have been exercised during your requirements based testing. Further, this means you can ensure that every call made to a barrier has been covered by your test suite.
Further information on code coverage developments are in an earlier blog post: What are the implications of multi-core devices on code coverage?
Visualization of Results
Visualization of task traces provides a simple mechanism to spot discrepancies in how a task is executing, such as multiple interrupts or priority inversion. Extending this to show multiple cores side by side, also means that synchronisation issues can be easily spotted. A large innovation from the project was development of the RapiTask tool (now part of RVS 3.2) to visualize traces on multiple cores, with data and task parallelization supported.
WCET for Multi-core
One of the biggest challenges for multi-core is measuring the worst case response time without returning overly pessimistic results. The pessimism is introduced when calculating lock waiting times during critical sections of code. The naïve assumption is that the worst case calculation for each thread needs to take into consideration the WCET from all the different threads that could also request that lock. What we found is that this level of pessimism can be reduced significantly if we only include the time spent in critical sections of the threads. We have developed extensions to RapiTime which take this into account, leading to tighter WCET results.
When parallelizing legacy software, it is important to identify data dependencies, such as global variables. During parMERASA we developed a tool to automatically find dependencies between code elements, based on global variable access. This is important to prevent read after write and write after read errors when the software is re-factored to multiple cores. The tool was used by the project partners to help during the parallelization process.
For more information on multi-core verification support please contact us.
For more information on the parMERASA projects please visit the project website.
All the slides from the parMERASA dissemincation event are available on their website.
White papers & webinars
Want to learn about common challenges and solutions in critical software verification? Our white papers and webinars may be just the thing:
- Multicore Timing Analysis for DO-178C
- Eight top code coverage questions in embedded avionics systems
- Seven Roadblocks to 100% structural coverage (and how to avoid them)
- Automating WCET Analysis for DO-178B & DO-178C
- Three steps to avoid software obsolescence in avionic systems
- CodeTEST® Replacement with RVS
- Multicore Timing Analysis for DO178 Projects Webinar