Timing analysis

Using Timed Finite Automata to define the timing behaviour of a system

What is Timed Finite Automata (TFA) and how can you use it to define the timing behaviour of your system?
Read More

Things that make real-time hard: DRAM refresh

Continuing the series on things that make real-time hard, this week we focus on DRAM refresh. What effect does a DRAM refresh have on the execution of code, and what can you do to resolve any issues?
Read More

How to use the System Clock to extract timing data from a TriCore timer

We work with many different embedded microcontrollers at Rapita Systems, so it’s useful to understand the need for timers and how to set up and use them. In most systems this involves interacting with several registers and some potentially confusing juggling of clock divisors and the like. However on a TriCore system there is a much easier option.
Read More

Things that make real-time hard - parallelization

Continuing our series of posts on what makes real-time hard, this week the focus is on parallelization. What issues arise when attempting to determine WCET of parallelised code and what can you do to overcome them?
Read More

Simple P4080 Benchmarking Reveals Arbitration Bias

We did some analysis on a Freescale P4080 multicore device with cache disabled (a previous blog post explains some of the challenges of doing real-time software in the presence of a cache). A benchmark run was set up with 100 executions of an industry standard benchmark. The same benchmark was used on both core 0 and core 1 of the P4080. Find out what happened next.
Read More

Pages