Want to learn more about multicore avionics certification?
Location: USA - Minneapolis (exact venue TBC)
Date: 23-24 June 2022
Location: Europe - Munich, Germany (exact venue TBC)
Date: Autumn 2022 (exact date TBC)
Rapita Systems will be delivering a limited series of technical, in-person training courses on the topic of CAST-32A (soon to be replaced by A(M)C 20-193). We have developed this training course to offer value for both beginners and experts alike.
Led by a team of multicore experts, the training will focus on practical approaches to satisfying CAST-32A objectives for both civil and defense multicore avionics projects.
Through a mix of theory and practical training, attendees will learn how to:
- Leverage industry-best approaches to CAST-32A compliance
- Interpret CAST-32A and what the objectives mean in practice
- Select the right multicore hardware for your project
- Characterize and quantify multicore interference in your platform
- Estimate worst-case-execution-time for multicore platforms
- Demonstrate robust partitioning in your multicore system
- Integrate CAST-32A evidence into your existing DO-178C workflow
- Comply with CAST-32A on Integrated Modular Avionics (IMA) systems
Full price: $799
Early bird: $699 (if booked 60+ days in advance of event)
- Day 1:
- Examine examples of final reports and certification deliverables early – how did we get here?
- Introduction to the challenges of using multicore processors for safety-critical projects
- Introduction to CAST-32A
- What’s needed in addition to DO-178C/ED-12C?
- How much effort is needed to comply with CAST-32A?
- Evaluating and selecting multicore hardware and RTOS
- Interference mitigation strategies
- What is robust partitioning for multicore systems?
- Multicore interference
- Sources of interference
- Quantifying interference and performance monitoring counters
- Verification of mitigation via Interference generators
- Demonstrating robust partitioning
- Integrated Modular Avionics (DO-297/ED-124) and CAST-32A
- How much testing is enough? Data collection infrastructure for CAST-32A verification
- Day 2:
- Ecosystem suppliers, dependencies and the Multicore Value Chain
- DO-178C planning for CAST-32A projects
- Plan for Aspects of Multicore Certification (PMAC)
- How to approach WCET calculation/estimation
- An overview of the Rapita CAST-32A workflow
- Why do we use this approach?
- End-to-end demonstration of generating CAST-32A evidence using the Rapita methodology
- Test requirements traced to system timing requirements
- Test definition (test cases/procedures) and execution
- Collection of timing metrics
- Estimation of WCET
- Formalizing evidence for cert.
Dr. Guillem Bernat
Dr. Guillem Bernat is one of the founders of Rapita Systems. He received his PhD in Computer Science from the Universitat de les Illes Balears in Spain in 1998, and then took a lecturing position at the Real-Time Systems Group at the University of York in the UK.
In 2004, he founded Rapita Systems to commercialize technology for measurement-based worst-case execution time analysis technology. Rapita Systems has grown to provide a set of software verification tools for safety-critical systems including timing analysis, WCET analysis and structural code coverage analysis to satisfy DO-178B/C and ISO-26262 objectives.
Dr. Bernat has more than 70 published papers in international conferences and journals, has lectured extensively in real-time systems, and is a frequent speaker at international conferences.
Dr. Steven VanderLeest
Steven H. VanderLeest is Principal Engineer for Multicore Systems at Rapita Systems Inc. He holds a Ph.D. from the University of Illinois. He was formerly a Professor of Engineering at Calvin University as well as COO and Vice-President of R&D at DornerWorks, Ltd., specializing in safety-critical electronics and software for avionics.
Dr. VanderLeest has publications spanning technical areas such as isolation and partitioning techniques for safety and security (including multicore interference channel analysis), computer performance measurement, and safety-critical design methodologies.
Dr. Vanderleest was the recipient of the Best Paper award for the 33rd Digital Avionics Systems Conference (DASC) for his paper titled “Timing Interrupts: Deterministic Asynchronicity in an ARINC 653 Environment.” He has been the principal investigator for multiple Small Business Innovation Research (SBIR) contracts, the US Navy, US Army, and the Defense Advanced Research Projects Agency (DARPA). VanderLeest holds multiple patents related to safety- and security-critical embedded technology.