Your browser does not support JavaScript! Skip to main content
Free 30-day trial DO-178C Handbook RapiCoupling Preview DO-178C Multicore Training Multicore Resources
Rapita Systems
 

Industry leading verification solutions

View All

Software Verification with RVS

RapiTest - Functional testing RapiCover - Coverage analysis RapiTime - Timing analysis RapiTask - RTOS scheduling visualization RapiCoverZero - Zero-footprint coverage analysis RapiTimeZero - Zero-footprint timing analysis RapiTaskZero - Zero-footprint scheduling analysis RVS Qualification Kits - Tool qualification for DO-178C RapiCouplingPreview - DCCC analysis

Multicore Verification with MACH178

MACH178 Core Pack - Getting started MACH178 Platform Pack - Platform evaluation MACH178 Resource Pack - Interference verification MACH178 Qualification Pack- Tool qualification

Product-related services

Tool Integration Training Consultancy Support

Other Solutions

RTBx - The ultimate data logging solution Sim68020 - Motorola 68020 Simulation

Using Our Solutions

RVS Development roadmap Product life cycle policy RVS Assurance issue policy

Latest from Rapita HQ

Latest news

Women in Tech Week - Elaine Batchelor Women in Tech Week - Elaine Batchelor on why soft skills matter and building quality teams from scratch
Women in Tech Week - Zoë Stephenson Women in Tech Week - Zoë Stephenson on on 25 years in tech, high-integrity software and making quality happen
Women in Tech Week - Hannah Jolly on making RVS easy and why representation matters
Women in Tech Week - Lily Gaunt on Roblox, real-world code and building cool things
View News

Latest from the Rapita blog

Introduction to Data Coupling and Control Coupling for DO-178C
The Evolution of DO-178 and ED-12 Standards
Retro gaming with the Sim68020
RVS gets a new timing analysis engine
View Blog

Latest discovery pages

Processor How to achieve multicore DO-178C certification with Rapita Systems
Plane How to achieve DO-178C certification with Rapita Systems
Military Drone Certifying Unmanned Aircraft Systems
control_tower DO-278A Guidance: Introduction to RTCA DO-278 approval
View Discovery pages

Upcoming events

Multicore Software Verification and Certification Training (Langton Aerospace Technology)
2026-10-27
Supporting Multicore Interference Analysis using Branch Traces
2026-11-24
View Events

Technical resources for industry professionals

Latest White papers

Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP
Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle
View White papers

Latest Videos

Supporting Multicore Interference Analysis using Branch Traces
Multicore Avionics (Aerospace Innovations)
AMACC Rev B & Multicore Certification: Key considerations for software verification in US defense programs
Certification-Ready Rust: GNAT Pro & RVS for Avionics Standards
View Videos

Latest Case studies

Case Study Front Cover
Multicore timing analysis support for ECSS-E-ST-40C R&D with MACH178
GMV case study front cover
GMV verify ISO26262 automotive software with RVS
Kappa: Verifying Airborne Video Systems for Air-to-Air Refueling using RVS
View Case studies

Other Resources

 Webinars

 Brochures

 Product briefs

 Technical notes

 Research projects

 Flyers

 Multicore resources

Discover Rapita

About us

The company menu

  • Customers
  • Partners & Distributors
  • Research projects
  • Contact us
  • Careers
  • Working at Rapita
  • Subscribe to newsletter

Industries

  Civil Aviation (DO-178C)   Military & Defense   Automotive (ISO 26262)   Space

Standards

  DO-178C   A(M)C 20-193

US office


info@rapitasystems.com Rapita Systems, Inc., 41131 Vincenti Ct., Novi, MI 48375, USA

UK office

+44 (0)1904 413945
info@rapitasystems.com Rapita Systems Ltd., Atlas House, Osbaldwick Link Road, York, YO10 3JB, UK

Spain office

+34 93 351 02 05
info@rapitasystems.com Rapita Systems S.L., Parc UPC, Edificio K2M, c/ Jordi Girona, 1-3, Barcelona 08034, Spain
Back to Top

Installing Targetlink 2.6, GCC 2.95.2 and Axiom MPC555

2010-08-12

We've had this web page up on the Rapita Systems website for some time now. As it seems to be of interest to quite a few visitors, we've decided to move it into the blog.

Installing GCC 2.95.2 for Targetlink (Windows)

This procedure details a step by step installation of GCC 2.95.2 for Targetlink 2.6 on Windows. 1. Download: cygwin; PowerPC GNU Toolkit v2.05; newlib-1.13.0.zip 2. Install cygwin c:\cygwin 3. Install PpcElfInstall.exe in c:\cygwin 4. Unzip newlib-1.13.0.zip in c:\cygwin\home\user 5. Open a cygwin console (Icon "Macraigor Cygwin Shell" on the desktop) 6. Start a cygwin console and fix the broken spec file: dos2unix.exe /usr/local/lib/gcc-lib/powerpc-elf/2.95.2/specs 7. Start a cygwin console and compile and install newlib:

cd
mkdir newlib_compile
cd newlib_compile
../newlib-1.13.0/configure --target=powerpc-elf
make
make install

Installing Targetlink 2.6 with GCC for MPC555 (Windows)

This procedure details a step-by-step installation of dSpace Targetlink 2.6 for a Axiom MPC555 Board and GCC on Windows. 1. Execute TL2.0.6_Setup.exe (found on Targetlink 2.6 Install CD) and follow the instructions 2. Install gcc for targetlink. (See the "how to" above) 3. Execute the file TL206_TSM_CME555_GNU2952.exe (should be provided in directory GNU/gcc_package/TSMCME555GNU/ TL206_TSM-CME555-GNU2952) 4. Edit the file C:\dSPACE\matlab\TL\Config\tl_global_options.m After "% insert list of generic target code generation modules here ..." , add :

i = i+1;
codeopt(i).name = 'Generic MPC5XX/GNU2952';
codeopt(i).targetDLL = 'AnsiTarget.dll';
codeopt(i).target = 'Generic';
codeopt(i).cc = ;
codeopt(i).targetDir = 'SrcFiles\MPC5xx\GNU2952';

After "% insert list of target simulation configurations here ...", add :

i = i+1;
simconfig(i).name = 'CME555/GNU2952';
simconfig(i).board = 'CME555';
simconfig(i).cc = 'GNU2952';
simconfig(i).myC = 'MPC5XX';
simconfig(i).config = 'TLSerPort.xml';
simconfig(i).makefile = 'MakeFile.mk';
simconfig(i).compilerRootEnv = 'MPC5XX_GNU2952_ROOT';

5. Set the environment variable MPC5XX_GNU2952_ROOT=c:\cygwin\usr\local 6. Add c:\cygwin\bin to the PATH variable 7. Edit the file C:\dSPACE\matlab\TL\SimFiles\CME555\GNU2952\makefile.mk as follows:

# ------------------------------------------------------
# Define environment variables
# ------------------------------------------------------
%setenv TMPDIR = $(D_WORK)
%setenv COMPILER_PATH = $(COMP_ROOT)\bin\
%setenv LIBRARY_PATH = $(COMP_ROOT)\lib\gcc-lib\powerpc-elf\2.95.2\include
%setenv C_INCLUDE_PATH = $(COMP_ROOT)\lib\gcc-lib\powerpc-elf\2.95.2\include
%setenv path = $(COMP_ROOT)\bin
[...]
# ------------------------------------------------------
# Specify tools
# ------------------------------------------------------
CC = $(COMP_ROOT)\bin\powerpc-elf-gcc.exe # compiler
AS = $(COMP_ROOT)\bin\powerpc-elf-as.exe # assembler
LD = $(COMP_ROOT)\bin\powerpc-elf-ld.exe # linker
CV = $(COMP_ROOT)\bin\powerpc-elf-objcopy.exe # object converter
PA = $(TL_ROOT)\exe\TLawk.exe # AWK

8. Finally, fix the .h files so that they can be used by cpp (unixstyle end of line). In a cygwin console:

cd /cygdrive/c/dSpace
find . -name *.h -exec dos2unix {} \;

Troubleshooting with Targetlink 2.6, GCC 2.95.2 and Axiom MPC555 Q: "Cmd timeout" error received after downloading the SW to the board A: Change the serial driver of the board to 'polling mode'. To do so, edit file comm_drv.c in c:\dSpace\matlab\TL\SimFiles\CME555\GNU2952:

#define POLLING
//#undef POLLING

Q: "Could not find file.c" error while building the target

A: This usually happens because the cygwin DLL can not be found. Even if c:\cygwin\bin is in the path, it may not find it. Workaround: Manually copy it on the current directory. Maybe launching a cygwin window, and therefore forcing loading the DLL can solve the problem.

DO-178C webinars

DO178C webinars

White papers


Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP
Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle

A Commercial Solution for Safety-Critical Multicore Timing Analysis
  • Solutions
    • Rapita Verification Suite
    • RapiTest
    • RapiCover
    • RapiTime
    • RapiTask
    • MACH178
  • Latest
  • Latest menu

    • News
    • Blog
    • Events
    • Videos
  • Success Stories
  • Success Stories Menu

    • Airbus Defence & Space
    • BAE Systems
    • Cobham
    • Collins Aerospace
    • Leonardo
  • Downloads
  • Downloads menu

    • Brochures
    • Webinars
    • White Papers
    • Case Studies
    • Product briefs
    • Technical notes
    • Software licensing
  • Company
  • Company menu

    • About Rapita
    • Careers
    • Customers
    • Industries
    • Locations
    • Partners
    • Research projects
    • Contact
  • Discover
    • Multicore Timing Analysis
    • Worst Case Execution Time
    • WCET Tools
    • Code coverage for Ada, C & C++
    • MC/DC Coverage
    • Verifying additional code for DO-178C
    • Data Coupling & Control Coupling
    • DO-178C
    • AC 20-193 and AMC 20-193
    • Certifying eVTOL
    • Certifying UAS

All materials © Rapita Systems Ltd. 2026 - All rights reserved | Privacy information | Trademark notice Subscribe to our newsletter