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RapiTest - Functional testing for critical software
RapiCover - Low-overhead coverage analysis for critical software
RapiTime - In-depth execution time analysis for critical software
RapiTask - RTOS scheduling visualization
RVS Qualification Kits - Tool qualification for DO-178 B/C and ISO 26262 projects
RapiCouplingPreview - DCCC analysis
MACH178 - Multicore Avionics Certification for High-integrity DO-178C projects
MACH178 Foundations - Lay the groundwork for A(M)C 20-193 compliance
RapiDaemons - Analyze interference in multicore systems
RTBx - The ultimate data logging solution
Sim68020 - Simulation for the Motorola 68020 microprocessor
Data Coupling & Control Coupling
Training
Consultancy
Tool Integration
Support
RVS 3.24 accelerates multicore software verification
Rapita Systems and Avionyx Announce Strategic Partnership to Offer Best-in-class Avionics Solutions
RVS 3.23 Launched
Rapita System Announces New Distribution Partnership with COONTEC
RVS gets a new timing analysis engine
How to measure stack usage through stack painting with RapiTest
What does AMACC Rev B mean for multicore certification?
How emulation can reduce avionics verification costs: Sim68020
How to achieve multicore DO-178C certification with Rapita Systems
How to achieve DO-178C certification with Rapita Systems
Certifying Unmanned Aircraft Systems
DO-278A Guidance: Introduction to RTCA DO-278 approval
Test what you fly - Real code, Real Conditions Webinar
Avionics Certification Q&A: CERT TALK
XPONENTIAL 2026
DO-178C Multicore In-person Training (Heathrow)
Zero-footprint RVS tools such as RapiCoverZero reconstruct information on the behavior of an application when it runs by using branch trace information captured from the platform the application is running on and combining this with information obtained from a disassembly of the application. Visit our platform support page to learn more.
68k
Instruction sets
Zero-footprint RVS tools can analyze disassembled code for the 68k instruction set.
When code has been disassembled, Platform Support Packages (PSPs) must be able to understand the instruction set of the object code so they can parse it before it is used for subsequent analysis by zero-footprint RVS tools.
We can develop support for other instruction sets. For more information, contact us at
AArch64
Instruction sets
Zero-footprint RVS tools can analyze disassembled code for the AArch64 instruction set.
When code has been disassembled, Platform Support Packages (PSPs) must be able to understand the instruction set of the object code so they can parse it before it is used for subsequent analysis by zero-footprint RVS tools.
We can develop support for other instruction sets. For more information, contact us at
Ada
Programming languages
RVS can be used to verify Ada code for requirements-based testing, structural coverage, execution time and scheduling behavior.
AdaCore Ravenscar Profile
RTOS
RVS supports the verification of code using AdaCore Ravenscar Profile.
Compilers
RVS supports the AdaMULTI compiler.
CPU
RVS can be used to analyze software running on Analog Devices CPUs.
RVS tools can be used to analyze software run on any host operating system or embedded target (as long as a communication channel is available). The following is a non-exhaustive list of Analog Devices CPUs we have worked with:
- Blackfin
- SHARC
- SigmaDSP
- TigerSHARC
- ADSP-21xx
Model-Based Design
RVS helps you supplement the evidence you need to verify critical software developed using ANSYS® SCADE® models.
CPU
RVS can be used to analyze software running on Arm CPUs.
RVS tools can be used to analyze software run on any host operating system or embedded target (as long as a communication channel is available). The following is a non-exhaustive list of Arm CPUs we have worked with:
- ARM7
- ARM9
- ARM10
- ARM11
- Cortex-M
- Cortex-R
- Cortex-A
Arm Compiler
Compilers
Zero-footprint RVS is compatible with object code compiled by the Arm Compiler
Platform Support Packages (PSPs) must be able to disassemble executables for further analysis. Typically, tools required for this are supplied as part of a toolchain unique to each compiler.
We can develop support for other compilers. For more information, contact us at
Compilers
RVS supports the Arm DS-5 compiler.
Arm instruction set
Instruction sets
Zero-footprint RVS tools can analyze disassembled code for the arm instruction set.
When code has been disassembled, Platform Support Packages (PSPs) must be able to understand the instruction set of the object code so they can parse it before it is used for subsequent analysis by zero-footprint RVS tools.
We can develop support for other instruction sets. For more information, contact us at
Assembly
Programming languages
RVS can be used to verify Assembly code for structural coverage, execution time and scheduling behavior.
RTOS
RVS supports the verification of code using ASTERIOS (previously known as Krono-Safe ASTERIOS).
CPU
RVS can be used to analyze software running on Atmel CPUs.
RVS tools can be used to analyze software run on any host operating system or embedded target (as long as a communication channel is available). The following is a non-exhaustive list of Atmel CPUs we have worked with:
- AT90CAN128
AUTOSAR Adaptive Platform
RTOS
RVS supports the verification of code using AUTOSAR Adaptive Platform.
Software Configuration Management (SCM)
RVS tools are designed to work in Software Configuration Management tools such as Azure DevOps.
Software Configuration Management (SCM)
You can run RVS automatically through the Bamboo continuous integration server.
Bare Metal
RTOS
RVS (including zero-footprint tools) supports the verification of code running on Bare Metal (no OS)
RTOS
RVS supports the verification of code using Blackberry QNX.
Borland C++
Compilers
RVS supports the Borland C++ compiler.
C
Programming languages
RVS can be used to verify C code for requirements-based testing, structural coverage, execution time and scheduling behavior.
C++
Programming languages
RVS can be used to verify C++ code for requirements-based testing, structural coverage, execution time and scheduling behavior.
CC-RH850
Compilers
Zero-footprint RVS is compatible with object code compiled by the CC-RH850 compiler
Platform Support Packages (PSPs) must be able to disassemble executables for further analysis. Typically, tools required for this are supplied as part of a toolchain unique to each compiler.
We can develop support for other compilers. For more information, contact us at
Clang
Compilers
Zero-footprint RVS is compatible with object code compiled by the Clang compiler
Platform Support Packages (PSPs) must be able to disassemble executables for further analysis. Typically, tools required for this are supplied as part of a toolchain unique to each compiler.
We can develop support for other compilers. For more information, contact us at
Cobertura
Software Configuration Management (SCM)
RapiCover lets you export structural coverage results in a Cobertura format.
RTOS
RVS has an out-of-the-box integration with DDC-I's Deos operating system.
Requirements traceability
RapiTest lets you import requirements from DOORS through ReqIF.
RTOS
RVS supports the verification of code using ERIKA Enterprise.
CPU
RVS can be used to analyze software running on ESA CPUs.
RVS tools can be used to analyze software run on any host operating system or embedded target (as long as a communication channel is available). The following is a non-exhaustive list of ESA CPUs we have worked with:
- LEON2
RTOS
RVS (including zero-footprint tools) support the verification of code using ESOL eMCOS.
For it to be possible to analyze executables generated by a platform by zero-footprint RVS tools, it must be possible to collect information on context switches made during software execution. Whether this is possible or not depends on the real-time operating system (RTOS) used and its configuration. Platform Support Packages must be able to understand context switch information to support further analysis of an executable by zero-footprint RVS tools.
We can develop support for other real-time operating systems. For more information, contact us at
RTOS
RVS (including zero-footprint tools) supports the verification of code using FreeRTOS.
For it to be possible to analyze executables generated by a platform by zero-footprint RVS tools, it must be possible to collect information on context switches made during software execution. Whether this is possible or not depends on the real-time operating system (RTOS) used and its configuration. Platform Support Packages must be able to understand context switch information to support further analysis of an executable by zero-footprint RVS tools.
We can develop support for other real-time operating systems. For more information, contact us at
CPU
RVS can be used to analyze software running on FRONTGRADE Gaisler (previously known as Cobham Gaisler) CPUs.
RVS tools can be used to analyze software run on any host operating system or embedded target (as long as a communication channel is available). The following is a non-exhaustive list of FRONTGRADE Gaisler CPUs we have worked with:
- LEON3
- LEON4
G++
Compilers
RVS supports the G++ compiler.
Compilers
RVS supports the GCC.
GCC
Compilers
Zero-footprint RVS is compatible with object code compiled by the GCC compiler
Platform Support Packages (PSPs) must be able to disassemble executables for further analysis. Typically, tools required for this are supplied as part of a toolchain unique to each compiler.
We can develop support for other compilers. For more information, contact us at
Software Configuration Management (SCM)
RVS tools are designed to work in Software Configuration Management tools such as GitHub.
Software Configuration Management (SCM)
You can run RVS automatically through continuous integration pipelines in GitLab.
GNAT GPL
Compilers
RVS supports the AdaCore GNAT GPL compiler.
GNAT Pro
Compilers
RVS supports the AdaCore GNAT Pro compiler.
Green Hills Integrity
RTOS
RVS supports the verification of code using Green Hills Integrity.
CPU
RVS can be used to analyze software running on IBM CPUs.
RVS tools can be used to analyze software run on any host operating system or embedded target (as long as a communication channel is available). The following is a non-exhaustive list of IBM PowerPC implementations we have worked with:
- G1 (601)
- G2 (602, 603, 604, 620)
- G3 (740/750)
- 7xx/750 family
- G5/970 series
- 401
- 403
- 405
- 440 range
IBM Engineering Rhapsody
Model-Based Design
CPU
RVS can be used to analyze software running on Infineon CPUs.
RVS tools can be used to analyze software run on any host operating system or embedded target (as long as a communication channel is available). The following is a non-exhaustive list of Infineon CPUs we have worked with:
- XE166 family
- XC 2000 family
- C166 family
- TriCore
- TriCore Aurix
- TriCore Aurix Gen2
- XMC1000
iSYSTEM
Debuggers
RVS tools support software verification using branch traces collected from the iSYSTEM debuggers.
Using a trace port (NEXUS or ARM‑ETM), RVS can collect traces via the following iSYSTEM debuggers, which monitor writes made to a specific register or memory location:
- iC3000GT and iTRACE GT
- iC5000
Requirements traceability
RapiTest has a dedicated integration with the Jama Connect® requirements management and traceability tool
Software Configuration Management (SCM)
You can run RVS automatically through the Jenkins continuous integration server.
Software Configuration Management (SCM)
RapiTest lets you export functional test results in the JUnit format
Lauterbach TRACE32
Debuggers
Zero-footprint RVS tools are with branch traces collected using the Lauterbach TRACE32.
For it to be possible to analyze executables generated by a platform by zero-footprint RVS tools, it must be possible to collect a branch trace from the platform*. Some targets generate branch traces by default, for example:
- Boards that have been developed to meet at least Class 2 of the Nexus message-based trace protocol
- ARM boards including an ARM ETM component
- Custom boards developed to produce branch traces
A debugger may be used to collect these branch traces from the target. Each Platform Support Package (PSP) is designed to support branch traces collected by a specific debugger.
We can develop support for other debuggers and simulators. For more information, contact us at
RTOS
RVS supports the verification of code using LynxOS.
RTOS
RVS supports the verification of code using LynxSecure.
MachineWare
Simulators
RVS tools support verifying code executed on MachineWare simulators.
MachineWare simulators integrate with Rapita tools like physical hardware and can be used to gain deep insights even before first hardware prototypes are available. Such as:
- SIM-A (Arm simulator)
- SIM-V (RISC-V simulator)
MaRTE OS
RTOS
RVS supports the verification of code using MaRTE OS.
Model-Based Design
RTOS
RVS supports the verification of code using μC/OS.
MICROSAR
RTOS
RVS supports the verification of code using MICROSAR.
Microsoft TFS
Software Configuration Management (SCM)
RVS tools are designed to work in Software Configuration Management tools such as Microsoft TFS.
Compilers
RVS supports the MULTI (C/C++) compiler.
CPU
RVS can be used to analyze software running on Freescale/NXP CPUs.
RVS tools can be used to analyze software run on any host operating system or embedded target (as long as a communication channel is available). The following is a non-exhaustive list of Freescale (NXP) CPUs we have worked with:
- 68000
- 680x0
- ColdFire
- M-CORE
- Power Architecture (MPC5xx, MPC55xx, MPC56xx, MPC57xx)
- ARM Cortex-M microcontrollers (Kinetis E series, Kinetis K series, Kinetis L series, Kinetis M series, Kinetis W series).
- 56k DSP family
- QorIQ (P2010, P2020, P4080, P5010, P5020, P5021, P5040, T2080)
PARTNER-Jet2
Debuggers
Zero-footprint RVS tools are with branch traces collected using the PARTNER-Jet2.
For it to be possible to analyze executables generated by a platform by zero-footprint RVS tools, it must be possible to collect a branch trace from the platform*. Some targets generate branch traces by default, for example:
- Boards that have been developed to meet at least Class 2 of the Nexus message-based trace protocol
- ARM boards including an ARM ETM component
- Custom boards developed to produce branch traces
A debugger may be used to collect these branch traces from the target. Simulators may generate branch traces, or it may be possible to modify them to do so. Each Platform Support Package (PSP) is designed to support branch traces collected by a specific debugger or from a specific simulator. The debuggers and simulators PSPs already support are listed below:
We can develop support for other debuggers and simulators. For more information, contact us at
RTOS
RVS (including zero-footprint tools) supports the verification of code using SYSGO PikeOS.
For it to be possible to analyze executables generated by a platform by zero-footprint RVS tools, it must be possible to collect information on context switches made during software execution. Whether this is possible or not depends on the real-time operating system (RTOS) used and its configuration. Platform Support Packages must be able to understand context switch information to support further analysis of an executable by zero-footprint RVS tools.
We can develop support for other real-time operating systems. For more information, contact us at
Requirements traceability
RapiTest supports integration with the Polarion® ALM™ requirements management and traceability tool
PowerPC
Instruction sets
Zero-footprint RVS tools can analyze disassembled code for the PowerPC instruction set.
When code has been disassembled, Platform Support Packages (PSPs) must be able to understand the instruction set of the object code so they can parse it before it is used for subsequent analysis by zero-footprint RVS tools.
We can develop support for other instruction sets. For more information, contact us at
QEMU
Simulators
Zero-footprint RVS tools support the verification with branch traces generated using the a modified version of the QEMU simulator.
For it to be possible to analyze executables generated by a platform by zero-footprint RVS tools, it must be possible to collect a branch trace from the platform. Some targets generate branch traces by default, for example:
- Boards that have been developed to meet at least Class 2 of the Nexus message-based trace protocol
- ARM boards including an ARM ETM component
- Custom boards developed to produce branch traces
Simulators may generate branch traces, or it may be possible to modify them to do so. Each Platform Support Package (PSP) is designed to support branch traces collected from a specific simulator.
We can develop support for other debuggers and simulators. For more information, contact us at
Requirements traceability
RapiTest integrates with requirements management software that can produce ReqIF format results.
Requirements traceability
RapiTest lets you import requirements from Reqtify through ReqIF.
RH850
Instruction sets
Zero-footprint RVS tools can analyze disassembled code for the RH850 instruction set.
When code has been disassembled, Platform Support Packages (PSPs) must be able to understand the instruction set of the object code so they can parse it before it is used for subsequent analysis by zero-footprint RVS tools.
We can develop support for other instruction sets. For more information, contact us at
RI850V4
RTOS
RVS supports the verification of code using RI850V4.
RTOS
RVS supports the verification of code using RTEMS.
RTXC Quadros
RTOS
RVS supports the verification of code using RTXC Quadros.
SafeRTOS
RTOS
RVS (including zero-footprint tools) supports the verification of code using SafeRTOS.
For it to be possible to analyze executables generated by a platform by zero-footprint RVS tools, it must be possible to collect information on context switches made during software execution. Whether this is possible or not depends on the real-time operating system (RTOS) used and its configuration. Platform Support Packages must be able to understand context switch information to support further analysis of an executable by zero-footprint RVS tools.
We can develop support for other real-time operating systems. For more information, contact us at
Software Configuration Management (SCM)
RVS tools are designed to work in Software Configuration Management tools such as TeamCity.
CPU
RVS can be used to analyze software running on Texas Instruments CPUs.
RVS tools can be used to analyze software run on any host operating system or embedded target (as long as a communication channel is available). The following is a non-exhaustive list of TI CPUs we have worked with:
- TMS320C6x family
- TMS320C28x family
- TMS320F28x family
- TMS570 family
VISUM
Instruction sets
Zero-footprint RVS tools can analyze disassembled code for the VISUM instruction set.
When code has been disassembled, Platform Support Packages (PSPs) must be able to understand the instruction set of the object code so they can parse it before it is used for subsequent analysis by zero-footprint RVS tools.
We can develop support for other instruction sets. For more information, contact us at
Requirements traceability
RapiTest lets you import requirements from Visure through ReqIF.
Wind River Helix & VxWorks
RTOS
RVS supports the verification of code using Wind River Helix & VxWorks.
x86
Instruction sets
Zero-footprint RVS tools can analyze disassembled code for the x86 instruction set.
When code has been disassembled, Platform Support Packages (PSPs) must be able to understand the instruction set of the object code so they can parse it before it is used for subsequent analysis by zero-footprint RVS tools.
We can develop support for other instruction sets. For more information, contact us at
