Supporting Multicore Interference Analysis using Branch Traces

When developing software for multicore systems, certification standards such as DO-178C and A(M)C 20-193 require an in-depth understanding and analysis of multicore interference. Timing information captured from branch traces plays a critical role in this, providing verification evidence and Worst-Case Execution Time (WCET) analysis. 

In this webinar, Lauterbach and Rapita Systems demonstrate how resource usage metrics can be measured and analyzed directly from hardware branch traces using TRACE32^® PowerTrace and the Rapita Verification Suite (RVS). 

Agenda

In this 1 hour live webinar, you'll learn:

• Why resource usage information is essential for multicore interference analysis and certification
• How to extract and analyze resource usage data directly from hardware branch traces
• How TRACE32 PowerTrace and RVS can be used to visualize multicore interference on a Xilinx UltraScale+ platform
• The benefits of zero-instrumentation analysis for reducing verification effort and preserving application behavior
• How hardware trace-based verification can be applied to mixed-language Ada and Rust applications

Presenters

Dr. Sam Thompson - Multicore Engineering Team Lead @ Rapita Systems 
Dr. Sam Thompson is a Multicore Engineering Team Lead at Rapita System, and has a significant role in both the development of Rapita’s multicore solution as well as the delivery of customer projects on multicore platforms. Sam's professional background includes work on safety-critical automation projects, systems design, and the analysis of large disparate datasets. He received his PhD from the University of York for the analysis of sub-diffraction-limit light-scattering and dynamic interaction data from engineered nanoparticles.

Moritz Baumann - Embedded System Engineer @ Lauterbach
Moritz Baumann is an Embedded Systems Engineer at Lauterbach. He completed a master's degree in Electrical Engineering and conducted his thesis at Lauterbach, studying multicore interference using hardware performance counters captured in trace. Following his thesis, he joined Lauterbach as an Embedded Systems Engineer in 2025, where he is a member of the OS Awareness Team.