This seminar will consider how to use processors with multiple cores in a way that safety can be assured, and such that the resulting system can be certified against industry standards and guidelines. Critical systems, such as those used in avionics, are moving from single core processor to multiple core (multi-core) processor architectures. This enables a reduction in size, weight and power and the use of common processing platforms, reducing costs and allowing common spares. Software certification policies and guidance are currently evolving as experience is gained with creating certification evidence for multi-core processor architectures. There are some unique challenges for using multi-core processors in certified platforms and these will be highlighted and discussed, including the investigation of multi-core interference channels.
Dr. Guillem Bernat will deliver a talk titled "Rapita Systems Independently Verifying the effectiveness of RTOS Hypervisors at reducing Multicore Interference" .
Find out more about the event here.
Our research in multicore timing analysis has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 878752. All rights reserved. Legal Notice.