Your browser does not support JavaScript! Skip to main content
Free 30-day trial Customer portal Careers DO-178C Handbook
 
Rapita Systems
 

Industry leading verification tools & services

Rapita Verification Suite (RVS)

  RapiTest - Unit/system testing   RapiCover - Structural coverage analysis   RapiTime - Timing analysis (inc. WCET)   RapiTask - Scheduling visualization   RapiCoverZero - Zero footprint coverage analysis   RapiTimeZero - Zero footprint timing analysis   RapiTaskZero - Zero footprint scheduling analysis

Multicore verification

  MACH178   Multicore Timing Solution   RapiDaemons

Services

  V & V Services   Qualification   Training   Tool Integration  Support

Industries

  Aerospace (DO-178C)   Automotive (ISO 26262)   Space

Other

  RTBx   Mx-Suite   Software licensing   Product life cycle policy  RVS development roadmap

Latest from Rapita HQ

Latest news

RVS 3.18 Launched
Solid Sands partners with Rapita Systems
Danlaw Acquires Maspatechnologies - Expanding Rapita Systems to Spain
Rapita co-authored paper wins ERTS22 Best paper award
View News

Latest from the Rapita blog

Measuring response times and more with RapiTime
Why mitigating interference alone isn’t enough to verify timing performance for multicore DO-178C projects
There are how many sources of interference in a multicore system?
Supporting modern development methodologies for verification of safety-critical software
View Blog

Latest discovery pages

do178c DO-178C Guidance: Introduction to RTCA DO-178 certification
matlab_simulink MATLAB® Simulink® MCDC coverage and WCET analysis
code_coverage_ada Code coverage for Ada, C and C++
amc-20-193 AMC 20-193
View Discovery pages

Upcoming events

Aerospace Tech Week Europe 2023
2023-03-29
Aeromart Montreal 2023
2023-04-04
Certification Together International Conference
2023-05-10
View Events

Technical resources for industry professionals

Latest White papers

DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle
A Commercial Solution for Safety-Critical Multicore Timing Analysis
Compliance with the Future Airborne Capability Environment (FACE) standard
View White papers

Latest Videos

Streamlined software verification with RVS 3.18
Sequence analysis with RapiTime
Visualize call dependencies with RVS thumbnail
Visualize call dependencies with RVS
Analyze code complexity thumbnail
Analyze code complexity with RVS
View Videos

Latest Case studies

Supporting ISO 26262 ASIL D software verification for EasyMile
RapiCover’s advanced features accelerate the certification of military UAV Engine Control
Front cover of whitepaper collins
Delivering world-class tool support to Collins Aerospace
View Case studies

Other Downloads

 Webinars

 Brochures

 Product briefs

 Technical notes

 Research projects

Discover Rapita

Who we are

The company menu

  • About us
  • Customers
  • Distributors
  • Locations
  • Partners
  • Research projects
  • Contact us

US office

+1 248-957-9801
info@rapitasystems.com
Rapita Systems, Inc.
41131 Vincenti Ct.
Novi
MI 48375
USA

UK office

+44 (0)1904 413945
info@rapitasystems.com
Rapita Systems Ltd.
Atlas House
Osbaldwick Link Road
York, YO10 3JB
UK

Spain office

+34 930 46 42 72
info@rapitasystems.com
Rapita Systems S.L.
Parc UPC, Edificio K2M
c/ Jordi Girona, 1-3, Office 306-307
Barcelona 08034
Spain

Working at Rapita

Careers

Careers menu

  • Current opportunities & application process
  • Working at Rapita
Back to Top

DO-178C - Stage of Involvement 2

Breadcrumb

  1. Home
  2. Blog
  3. DO-178C - Stage of Involvement 2
2022-03-09

SOI #2 - Development Review

After SOI #1, the next step is to develop your product. The first step in Development is to define the high-level requirements of your code. Later in Development, you will define low-level requirements. Developing high-level requirements involves refining the context of system requirements allocated to software and defining any software-specific requirements that do not map to system requirements as derived requirements. While defining both high and low-level requirements, you should ensure that you follow the processes you agreed to follow in your PSAC – your certification authority is likely to check that you have done so during future SOIs.

DO-178 Development Review

When your requirements are available, the next step is to design the architecture of your software and define its low-level requirements in order to define a system that can meet the high-level requirements you have identified. Design in DO-178C is the combination of architecture and low-level requirements. You will need to follow the design standards you said you would follow in your PSAC and provide evidence that you have done this.

When your requirements and design are ready, the next step will be to implement your product in code. This is comparatively only a small part of the overall compliance process, usually taking 5% or less of overall effort. The decisions you make on how to implement your product can have major effects on your verification later on. These can make your verification much easier or much more difficult, and as a result cause your project to either run smoothly or incur delays. As verification takes much more effort than implementation, it’s worth considering the effects your decisions will have and making decisions that will reduce your verification effort.

Here are a few things you may want to consider:

  • Choice of programming language(s)
  • Choice of coding standard(s)
  • Choice of hardware platform and operating system
  • Choice of compiler and compiler options
  • Use of emerging technologies (GPUs, multi-core processors etc.)
DO178C-SOI2

Before you have finished your Development, but when you have examples of each of your development artifacts (typically 60%-80% of your total expected artifacts), you should conduct SOI #2 with your certification authority. SOI #2 focuses on the development process and artifacts, but the review also considers verification processes that should be running concurrently with Development – specifically, the review activities being implemented. SOI #2 may also look forward to the verification phase to see if there are any examples where verification activities have provided feedback to development activities. This may include, for example, test case development or test environment development providing feedback to your requirements and design processes to ensure that test activities can completely verify the functionality expressed in your requirements and design.

Learn more about DO-178C by downloading the free 70-page handbook here.

DO-178C webinars

DO178C webinars

White papers

DO178C Handbook Efficient Verification Through the DO-178C Life Cycle
A Commercial Solution for Safety-Critical Multicore Timing Analysis
Compliance with the Future Airborne Capability Environment (FACE) standard
5 key factors to consider when selecting an embedded testing tool

Related blog posts

DO-178C - Stage of Involvement 4

.
2022-04-06

DO-178C - Stage of Involvement 3

.
2022-03-23

DO-178C - Stage of Involvement 1

.
2022-03-01

DO-178C Blog Series: Introduction to DO-178C

.
2022-01-17

Pagination

  • Current page 1
  • Page 2
  • Page 3
  • Page 4
  • Page 5
  • Next page Next ›
  • Last page Last »
  • Solutions
    • Rapita Verification Suite
    • RapiTest
    • RapiCover
    • RapiTime
    • RapiTask
    • MACH178

    • Verification and Validation Services
    • Qualification
    • Training
    • Integration
  • Latest
  • Latest menu

    • News
    • Blog
    • Events
    • Videos
  • Downloads
  • Downloads menu

    • Brochures
    • Webinars
    • White Papers
    • Case Studies
    • Product briefs
    • Technical notes
    • Software licensing
  • Company
  • Company menu

    • About Rapita
    • Careers
    • Customers
    • Distributors
    • Industries
    • Locations
    • Partners
    • Research projects
    • Contact
  • Discover
    • AMC 20-193
    • What is CAST-32A?
    • Multicore Timing Analysis
    • MC/DC Coverage
    • Code coverage for Ada, C & C++
    • Embedded Software Testing Tools
    • Aerospace Software Testing
    • Automotive Software Testing
    • Certifying eVTOL
    • DO-178C
    • WCET Tools
    • Worst Case Execution Time
    • Timing analysis (WCET) & Code coverage for MATLAB® Simulink®

All materials © Rapita Systems Ltd. 2023 - All rights reserved | Privacy information | Trademark notice Subscribe to our newsletter