Your browser does not support JavaScript! Skip to main content
Free 30-day trial DO-178C Handbook RapiCoupling Preview DO-178C Multicore Training Multicore Resources
Rapita Systems
 

Industry leading verification solutions

View All

Software Verification with RVS

RapiTest - Functional testing RapiCover - Coverage analysis RapiTime - Timing analysis RapiTask - RTOS scheduling visualization RapiCoverZero - Zero-footprint coverage analysis RapiTimeZero - Zero-footprint timing analysis RapiTaskZero - Zero-footprint scheduling analysis RVS Qualification Kits - Tool qualification for DO-178C RapiCouplingPreview - DCCC analysis

Multicore Verification with MACH178

MACH178 Core Pack - Getting started MACH178 Platform Pack - Platform evaluation MACH178 Resource Pack - Interference verification MACH178 Qualification Pack- Tool qualification

Product-related services

Tool Integration Training Consultancy Support

Other Solutions

RTBx - The ultimate data logging solution Sim68020 - Motorola 68020 Simulation

Using Our Solutions

RVS Development roadmap Product life cycle policy RVS Assurance issue policy

Latest from Rapita HQ

Latest news

Text: Whats New in RVS 3.25. Image: Double decker commercial airliner taking off from a runway with an overlay of code RVS 3.25 brings improved zero-footprint analysis to more platforms
Rapita Systems Collaborates with Wind River to Break the Multicore Certification Barrier
MACH178 Rapita Systems Launches Next Generation of MACH178 for Multicore
RVS 3.24 accelerates multicore software verification
View News

Latest from the Rapita blog

Introduction to Data Coupling and Control Coupling for DO-178C
The Evolution of DO-178 and ED-12 Standards
Retro gaming with the Sim68020
RVS gets a new timing analysis engine
View Blog

Latest discovery pages

Processor How to achieve multicore DO-178C certification with Rapita Systems
Plane How to achieve DO-178C certification with Rapita Systems
Military Drone Certifying Unmanned Aircraft Systems
control_tower DO-278A Guidance: Introduction to RTCA DO-278 approval
View Discovery pages

Upcoming events

DASC 2026
2026-09-13
DO-178C Multicore Virtual Training
2026-09-29
HISC 2026
2026-10-13
Supporting Multicore Interference Analysis using Branch Traces
2026-11-24
View Events

Technical resources for industry professionals

Latest White papers

Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP
Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle
View White papers

Latest Videos

Supporting Multicore Interference Analysis using Branch Traces
Multicore Avionics (Aerospace Innovations)
AMACC Rev B & Multicore Certification: Key considerations for software verification in US defense programs
Certification-Ready Rust: GNAT Pro & RVS for Avionics Standards
View Videos

Latest Case studies

Case Study Front Cover
Multicore timing analysis support for ECSS-E-ST-40C R&D with MACH178
GMV case study front cover
GMV verify ISO26262 automotive software with RVS
Kappa: Verifying Airborne Video Systems for Air-to-Air Refueling using RVS
View Case studies

Other Resources

 Webinars

 Brochures

 Product briefs

 Technical notes

 Research projects

 Flyers

 Multicore resources

Discover Rapita

About us

The company menu

  • Customers
  • Partners & Distributors
  • Research projects
  • Contact us
  • Careers
  • Working at Rapita
  • Subscribe to newsletter

Industries

  Civil Aviation (DO-178C)   Military & Defense   Automotive (ISO 26262)   Space

Standards

  DO-178C   A(M)C 20-193

US office


info@rapitasystems.com Rapita Systems, Inc., 41131 Vincenti Ct., Novi, MI 48375, USA

UK office

+44 (0)1904 413945
info@rapitasystems.com Rapita Systems Ltd., Atlas House, Osbaldwick Link Road, York, YO10 3JB, UK

Spain office

+34 93 351 02 05
info@rapitasystems.com Rapita Systems S.L., Parc UPC, Edificio K2M, c/ Jordi Girona, 1-3, Barcelona 08034, Spain
Back to Top

Getting TriCore PCP inline assembly right

2010-06-03

This macro (see below) toggles (0 becomes 1, 1 becomes 0) one of eight output pins of the Infineon TriCore 1797 port P9 by writing the appropriate value to the register P9_OMR. It uses an assembly string composed from string literals in the macro body and its "stringized" argument, #Pin, which is a value in the range 0..7. The final part of the inline assembly construct is the "clobber list", the list of registers changed (and not restored) by the assembly code. This macro is automatically inserted into PCP code by the RapiTime code instrumenter in order to monitor the different paths and times taken by software executing a number of tests (see RapiTime instrumentation).

#define RPT_TogglePin(Pin) __asm(               \
    "ldl.il r0,(1 << (" #Pin "))     \n\t"      \
    "ldl.iu r0,(1 << (" #Pin "))     \n\t"      \
    "ldl.iu r1,@HI(P9_OMR)           \n\t"      \
    "ldl.il r1,@LO(P9_OMR)           \n\t"      \
    "st.f  r0,[r1],size=32"                     \
    :::"r1","r0","r7")

It is not obvious that r7 is corrupted by the listed instructions. When we omitted r7 from the clobber list, the TASKING compiler generated code that, very efficiently, cached the result of a test in the Z flag, assuming that this flag was preserved by our RPT_TogglePin macro. However r7 contains the PRAM data pointer (DPTR) and the status flags, including the N and Z flags that are changed by the ldl instruction. When the compiled code read the corrupted Z flag immediately after the assembly code for RPT_TogglePin, the program failed, triggering an expensive debugging process. The fix was simply to add r7 to the clobber list, informing the compiler that r7 is not preserved by the inline assembly string and ensuring that it saves and restores the Z flag itself.

You have to include r7 in the clobber list for inline assembly unless you have checked each instruction to be sure that it affects neither DPTR nor the status flags.

DO-178C webinars

DO178C webinars

White papers


Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP
Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle

A Commercial Solution for Safety-Critical Multicore Timing Analysis

Related blog posts

Interesting microcontroller features: the PowerPC ISEL instruction

.
2014-01-23

Chaining two 16 bit timers together in STM32f4

.
2013-12-10

Reading large arrays with Vector CANape

.
2013-12-03

Setting up a free-running timer on the STM32 Discovery F4 board

.
2013-11-25

Pagination

  • First page « First
  • Previous page ‹ Previous
  • Page 1
  • Current page 2
  • Page 3
  • Page 4
  • Next page Next ›
  • Last page Last »
  • Solutions
    • Rapita Verification Suite
    • RapiTest
    • RapiCover
    • RapiTime
    • RapiTask
    • MACH178
  • Latest
  • Latest menu

    • News
    • Blog
    • Events
    • Videos
  • Success Stories
  • Success Stories Menu

    • Airbus Defence & Space
    • BAE Systems
    • Cobham
    • Collins Aerospace
    • Leonardo
  • Downloads
  • Downloads menu

    • Brochures
    • Webinars
    • White Papers
    • Case Studies
    • Product briefs
    • Technical notes
    • Software licensing
  • Company
  • Company menu

    • About Rapita
    • Careers
    • Customers
    • Industries
    • Locations
    • Partners
    • Research projects
    • Contact
  • Discover
    • Multicore Timing Analysis
    • Worst Case Execution Time
    • WCET Tools
    • Code coverage for Ada, C & C++
    • MC/DC Coverage
    • Verifying additional code for DO-178C
    • Data Coupling & Control Coupling
    • DO-178C
    • AC 20-193 and AMC 20-193
    • Certifying eVTOL
    • Certifying UAS

All materials © Rapita Systems Ltd. 2026 - All rights reserved | Privacy information | Trademark notice Subscribe to our newsletter