Rapita to present on multicore timing analysis at HiPEAC 2018
Rapita Systems' CEO, Dr. Guillem Bernat, will be presenting at the 6th international MCS workshop, which is hosted at HiPEAC on Tuesday 22nd January at the Manchester Central Convention Centre.
At the workshop, which explores the integration of mixed-criticality subsystems on multicore and manycore processors, Guillem will describe the difficulties of performing worst-case execution timing analysis on multicore systems, and how Rapita, together with the Barcelona Supercomputing Center, address these.
If you're attending the conference, be sure to catch his presentation, which will start at around 12.15 in room 8.
White papers & webinars
Want to learn about common challenges and solutions in critical software verification? Our white papers and webinars may be just the thing:
- Multicore Timing Analysis for DO-178C
- Eight top code coverage questions in embedded avionics systems
- Seven Roadblocks to 100% structural coverage (and how to avoid them)
- Automating WCET Analysis for DO-178B & DO-178C
- Three steps to avoid software obsolescence in avionic systems
- CodeTEST® Replacement with RVS
- Multicore Timing Analysis for DO178 Projects Webinar