PROARTIS is a small or medium scale focused research project (STREP) funded in part by the European Union’s Seventh Framework Programme (FP7). The aim of PROARTIS is to define new hardware and software architecture paradigms whose timing behavior can be analyzed with probabilistic techniques. These new paradigms move towards design principles that make both the execution environment and the RTOS aware of the hardware. At the same time, the application programmer is freed from dealing with hardware issues.
The hypothesis of the PROARTIS project is that randomized behavior in hardware enables probabilistic analysis techniques to verify critical timing behaviors for real-time embedded systems. The underlying objective of the PROARTIS project is not to completely remove pathological execution time cases from the system (which arguably is not possible), but instead to enable a probabilistic analysis that proves that those pathological cases can only arise with a negligible probability.
This will provide a substantial advancement over current methods, including static analysis techniques and testing that so far are unable to scale up to the size and complexity of next-generation embedded real-time systems. Unlike previous approaches that provide analyzability by using deterministic and hence predictable hardware and software components, PROARTIS provides analyzability by using a hardware and software components that provide independence by design.
This represents a shift with respect to previous approaches. Since both approaches are mutually exclusive, one of the aims of the project is to quantify and compare the two paradigms. PROARTIS will support the production of analyzable critical systems on modern and future advanced hardware features such as memory hierarchies and multi-core processors. Hence, PROARTIS will allow:
- Increased productivity by enabling programmers to develop more complex real-time software systems through timing-aware systems that reveal crucial timing details while dramatically simplifying analysis. For example, memory latencies will be predicted with less effort, requiring knowledge only of the total number of memory accesses, rather than exact memory addresses and memory access patterns.
- Increased performance and reduced costs by enabling critical systems to take full advantage of advanced hardware like deep memory hierarchies and multicore processors. This will permit designers to schedule more tasks inside a powerful processor (delivering them from the current task-weary attitude) also reducing the weight and the size of the whole system.
- Reduced time-to-market by enabling trustworthy WCET analyses for large-scale real-time systems that will dramatically reduce testing time.
The PROARTIS project started on 1st February 2010. The partners involved in the work are:
- Barcelona Supercomputing Center – Centro Nacional de Supercomputación
- Rapita Systems Ltd
- University of Padua
For further information, please visit: http://www.proartis-project.eu