To continue delivering regular performance improvements or general-purpose processors, manufacturers such as Freescale and ARM have turned to multi-core architectures. Multicore processors are now the norm in general-purpose devices such as laptops and mobile phones.
In the safety-critical software domain, multicore systems pose many new challenges during the certification process. One of the most difficult challenges is the calculation of the worst-case execution time of software, which must be achieved for certification of systems to meet safety guidelines such as DO-178C/ED-12C. Additional guidance on multicore timing in these contexts was released in the CAST-32A paper.
Approaches to timing analysis that are adequate for single core processors do not scale up to effective use on multicore systems. Manual methods are expensive, inaccurate and not easily repeatable, and no tool alone can provide adequate timing analysis estimates.
Rapita Systems' approach for performing timing analysis is offered in collaboration with the Barcelona Supercomputing Center and uses RapiTime to automate the capture and analysis of results from microbenchmarks written from experimental design. This approach provides the right balance of rigor, flexibility, precision and effort to deliver estimates of worst-case execution time that can be used even for the highest software criticality levels.