Danlaw Acquires Maspatechnologies - Expanding Rapita Systems to Spain
Rapita co-authored paper wins ERTS22 Best paper award
A look back on Rapita's Multicore DO-178C training in Huntsville
RVS 3.17 Launched
Why mitigating interference alone isn’t enough to verify timing performance for multicore DO-178C projects
There are how many sources of interference in a multicore system?
Supporting modern development methodologies for verification of safety-critical software
Flexible licensing software fit for modern working
DO-178C Guidance: Introduction to RTCA DO-178 certification
MATLAB® Simulink® MCDC coverage and WCET analysis
Code coverage for Ada, C and C++
AMC 20-193
Aerospace Tech Week Europe 2023
Certification Together International Conference
VeTeSS will develop standardized tools and methods for verification of the robustness of safety-relevant systems, particularly against transient common-cause faults.
The project is co-funded by the EU through the ARTEMIS Joint Undertaking, a pan-European research programme to strengthen Europe's position in embedded intelligence and systems.
The focus of VeTeSS is the strategically important automotive market. Since the safety of conventional and new electric/hybrid vehicles needs to be proven to allow wider adoption, which will in turn be an important contribution to carbon emissions reduction, new tools and methods which provide standardized data from verification and help meet ISO 26262 requirements are in demand.
The project is expected to improve the competitiveness of the European embedded hardware and software industry, raise the safety, quality and reliability of products, and enable innovative technologies to increase road user safety. Rapita Systems will develop new code coverage measurement tools to test the systems created by other partner organisations as the project continues. For more details visit the VeTeSS website.
