Your browser does not support JavaScript! Skip to main content
Free 30-day trial Customer portal Careers DO-178C Handbook
 
Rapita Systems
 

Industry leading verification tools & services

Rapita Verification Suite (RVS)

  RapiTest - Unit/system testing   RapiCover - Structural coverage analysis   RapiTime - Timing analysis (inc. WCET)   RapiTask - Scheduling visualization   RapiCoverZero - Zero footprint coverage analysis   RapiTimeZero - Zero footprint timing analysis   RapiTaskZero - Zero footprint scheduling analysis

Multicore verification

  MACH178   Multicore Timing Solution   RapiDaemons

Services

  V & V Services   Qualification   Training   Tool Integration  Support

Industries

  Aerospace (DO-178C)   Automotive (ISO 26262)   Space

Other

  RTBx   Mx-Suite   Software licensing   Product life cycle policy  RVS development roadmap

Latest from Rapita HQ

Latest news

RVS 3.18 Launched
Solid Sands partners with Rapita Systems
Danlaw Acquires Maspatechnologies - Expanding Rapita Systems to Spain
Rapita co-authored paper wins ERTS22 Best paper award
View News

Latest from the Rapita blog

Why mitigating interference alone isn’t enough to verify timing performance for multicore DO-178C projects
There are how many sources of interference in a multicore system?
Supporting modern development methodologies for verification of safety-critical software
Flexible licensing software fit for modern working
View Blog

Latest discovery pages

do178c DO-178C Guidance: Introduction to RTCA DO-178 certification
matlab_simulink MATLAB® Simulink® MCDC coverage and WCET analysis
code_coverage_ada Code coverage for Ada, C and C++
amc-20-193 AMC 20-193
View Discovery pages

Upcoming events

Aerospace Tech Week Europe 2023
2023-03-29
Aeromart Montreal 2023
2023-04-04
Certification Together International Conference
2023-05-10
View Events

Technical resources for industry professionals

Latest White papers

DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle
A Commercial Solution for Safety-Critical Multicore Timing Analysis
Compliance with the Future Airborne Capability Environment (FACE) standard
View White papers

Latest Videos

Streamlined software verification with RVS 3.18
Sequence analysis with RapiTime
Visualize call dependencies with RVS thumbnail
Visualize call dependencies with RVS
Analyze code complexity thumbnail
Analyze code complexity with RVS
View Videos

Latest Case studies

Supporting ISO 26262 ASIL D software verification for EasyMile
RapiCover’s advanced features accelerate the certification of military UAV Engine Control
Front cover of whitepaper collins
Delivering world-class tool support to Collins Aerospace
View Case studies

Other Downloads

 Webinars

 Brochures

 Product briefs

 Technical notes

 Research projects

Discover Rapita

Who we are

The company menu

  • About us
  • Customers
  • Distributors
  • Locations
  • Partners
  • Research projects
  • Contact us

US office

+1 248-957-9801
info@rapitasystems.com
Rapita Systems, Inc.
41131 Vincenti Ct.
Novi
MI 48375
USA

UK office

+44 (0)1904 413945
info@rapitasystems.com
Rapita Systems Ltd.
Atlas House
Osbaldwick Link Road
York, YO10 3JB
UK

Spain office

+34 930 46 42 72
info@rapitasystems.com
Rapita Systems S.L.
Parc UPC, Edificio K2M
c/ Jordi Girona, 1-3, Office 306-307
Barcelona 08034
Spain

Working at Rapita

Careers

Careers menu

  • Current opportunities & application process
  • Working at Rapita
Back to Top

How do I set up an MPC5xx IO port to collect data?

Breadcrumb

  1. Home
  2. Blog
  3. How do I set up an MPC5xx IO port to collect data?
2012-11-12

At Rapita, our main interest in writing to output ports of microcontrollers is to provide an efficient means of measuring code execution times or code coverage (via our RapiTime or RapiCover tools – both part of RVS). Typically, we’d have some way of logging the values written to the output port, for example the RTBx or a logic analyzer.

In common with many microcontrollers, the Freescale MPC5xx series microcontroller has a number of ports that can be configured for general purpose digital input or output, or other specific purposes. Possibilities for output ports include:

  • Queued Analog to Digital Converter Module (QADCM)
  • Queued Serial Multi Channel Module (QSMCM)
  • Modular IO System (MIOS) Parallel Port IO Submodule (MPIOSM)

Before data can be output through any port it is first necessary to:

  1. initialize the output pins as general purpose IO
  2. configure the port as output rather than input
  3. set the pin characteristics to match the signal being generated

Each IO port will have a number of associated registers that control the operation of that port that need to be set appropriately.

Within RVS, we normally initialize ports within the RVS_Init() routine, which must be called before any instrumentation is executed. To illustrate the configuration of one of the ports, we show an example RVS_Init() routine.

Most compilers are supplied with address definitions that allow register names to be used directly in the source code, however check your compiler and CPU documentation to be sure.

Here we consider how an instrumentation library can be written to output values through the QADCM. There are two QADC modules, each of which contain a pair of 8 bit ports that can be configured for output. The example RVS_Init() below shows how to initialise port A on QADC module A for output:

void RVS_Init()
{
   UMCR = 0;              /* high bus frequency       */
   PDMCR = 0x80000000uL;  /* normal slew rate for QAD */
   PORTQA_A = 0;          /* Initialise pins low      */
   DDRQA_A = 0xFF;        /* Set as output            */
}

The registers used are as follows:

  • UMCR UIMB Module Configuration Register. Used to configure the U-BUS to IMB3 interface to run at full speed.
  • PDMCR Pad Module Configuration Register. Used to set normal rather than slow slew rate.
  • PORTQA_A Port Data Register for port A on QADC module A.
  • DDRQA_A Port Data Direction Register for port A on QADC module A.

Once the port has been initialised, values can be written via the Port Data Register. For example, in RVS, instrumentation point IDs can be written by including the following definition in rvs_ipoint.h:

#define RVS_I( I ) ((void)(PORTQA_A = (I)))

DO-178C webinars

DO178C webinars

White papers

DO178C Handbook Efficient Verification Through the DO-178C Life Cycle
A Commercial Solution for Safety-Critical Multicore Timing Analysis
Compliance with the Future Airborne Capability Environment (FACE) standard
5 key factors to consider when selecting an embedded testing tool
  • Solutions
    • Rapita Verification Suite
    • RapiTest
    • RapiCover
    • RapiTime
    • RapiTask
    • MACH178

    • Verification and Validation Services
    • Qualification
    • Training
    • Integration
  • Latest
  • Latest menu

    • News
    • Blog
    • Events
    • Videos
  • Downloads
  • Downloads menu

    • Brochures
    • Webinars
    • White Papers
    • Case Studies
    • Product briefs
    • Technical notes
    • Software licensing
  • Company
  • Company menu

    • About Rapita
    • Careers
    • Customers
    • Distributors
    • Industries
    • Locations
    • Partners
    • Research projects
    • Contact
  • Discover
    • AMC 20-193
    • What is CAST-32A?
    • Multicore Timing Analysis
    • MC/DC Coverage
    • Code coverage for Ada, C & C++
    • Embedded Software Testing Tools
    • Aerospace Software Testing
    • Automotive Software Testing
    • Certifying eVTOL
    • DO-178C
    • WCET Tools
    • Worst Case Execution Time
    • Timing analysis (WCET) & Code coverage for MATLAB® Simulink®

All materials © Rapita Systems Ltd. 2023 - All rights reserved | Privacy information | Trademark notice Subscribe to our newsletter