Your browser does not support JavaScript! Skip to main content
Free 30-day trial DO-178C Handbook RapiCoupling Preview DO-178C Multicore Training Multicore Resources
Rapita Systems
 

Industry leading verification tools & services

Rapita Verification Suite (RVS)

  RapiTest - Unit/system testing  RapiCover - Structural coverage analysis  RapiTime - Timing analysis (inc. WCET)  RapiTask - Scheduling visualization  RapiCoverZero - Zero footprint coverage analysis  RapiTimeZero - Zero footprint timing analysis  RapiTaskZero - Zero footprint scheduling analysis  RapiCouplingPreview - DCCC analysis

Multicore Verification

  MACH178  MACH178 Foundations  Multicore Timing Solution  RapiDaemons

Engineering Services

  V&V Services  Data Coupling & Control Coupling  Object code verification  Qualification  Training  Consultancy  Tool Integration  Support

Industries

  Civil Aviation (DO-178C)   Automotive (ISO 26262)   Military & Defense   Space

Other

RTBx Mx-Suite Software licensing Product life cycle policy RVS Assurance issue policy RVS development roadmap

Latest from Rapita HQ

Latest news

SAIF Autonomy to use RVS to verify their groundbreaking AI platform
RVS 3.22 Launched
Hybrid electric pioneers, Ascendance, join Rapita Systems Trailblazer Partnership Program
Magline joins Rapita Trailblazer Partnership Program to support DO-178 Certification
View News

Latest from the Rapita blog

How to certify multicore processors - what is everyone asking?
Data Coupling Basics in DO-178C
Control Coupling Basics in DO-178C
Components in Data Coupling and Control Coupling
View Blog

Latest discovery pages

control_tower DO-278A Guidance: Introduction to RTCA DO-278 approval
Picture of a car ISO 26262
DCCC Image Data Coupling & Control Coupling
Additional Coe verification thumb Verifying additional code for DO-178C
View Discovery pages

Upcoming events

DASC 2025
2025-09-14
DO-178C Multicore In-person Training (Fort Worth, TX)
2025-10-01
DO-178C Multicore In-person Training (Toulouse)
2025-11-04
HISC 2025
2025-11-13
View Events

Technical resources for industry professionals

Latest White papers

Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP
Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle
View White papers

Latest Videos

Rapita Systems - Safety Through Quality
Simulation for the Motorola 68020 microprocessor with Sim68020
AI-driven Requirements Traceability for Faster Testing and Certification
Multicore software verification with RVS 3.22
View Videos

Latest Case studies

GMV case study front cover
GMV verify ISO26262 automotive software with RVS
Kappa: Verifying Airborne Video Systems for Air-to-Air Refueling using RVS
Supporting DanLaw with unit testing and code coverage analysis for automotive software
View Case studies

Other Resources

 Webinars

 Brochures

 Product briefs

 Technical notes

 Research projects

 Multicore resources

Discover Rapita

Who we are

The company menu

  • About us
  • Customers
  • Distributors
  • Locations
  • Partners
  • Research projects
  • Contact us

US office

+1 248-957-9801
info@rapitasystems.com
Rapita Systems, Inc.
41131 Vincenti Ct.
Novi
MI 48375
USA

UK office

+44 (0)1904 413945
info@rapitasystems.com
Rapita Systems Ltd.
Atlas House
Osbaldwick Link Road
York, YO10 3JB
UK

Spain office

+34 93 351 02 05
info@rapitasystems.com
Rapita Systems S.L.
Parc UPC, Edificio K2M
c/ Jordi Girona, 1-3
Barcelona 08034
Spain

Working at Rapita

Careers

Careers menu

  • Current opportunities & application process
  • Working at Rapita
Back to Top Contact Us

How to set up safe, portable interprocess communication without interrupt locks

Breadcrumb

  1. Home
2010-09-30

The approach described here allows non-blocking interprocess communication to take place on a single CPU, via a FIFO, circular buffer. I originally encountered this method of interprocess communication as part of the MASCOT design methodology, as a way of implementing the channel IDA.

To meet the requirements of providing safe interprocess communication without interrupt locks, the following must be true:

  • Both processes can access common memory
  • Communication is one-way, and occurs from one process/thread to another
  • It is possible to write the in/out indices as an atomic action (i.e. as one machine instruction)
  • It is possible to read the in/out indices as an atomic action
  • Writer never attempts to write to a full buffer
  • Reader never attempts to read from a buffer that doesn't contain valid data
  • Adding data into the buffer does not need to be atomic. That is, it is safe to store records or arrays into the queue

The approach relies upon a circular buffer consists of the following elements:

buffer: array of data with 2^n elements 
in, out: unsigned integers as indices with range 0 to (2^(n+1))-1 

Before reading and writing, it is important to test whether the queue is empty or full, respectively. All queue conditions can be found by looking at the result of the following expression:

 buffer_contents = (in - out) % (2^(n+1)) 

The results of this expression are as follows:

buffer_contents == 0: Queue empty
buffer_contents > 0 && buffer_contents < 2^n: Queue
        contains valid data 
buffer_contents == 2^n: Queue is full 
buffer_contents > 2^n: overrun has occurred 

Writing must only take place when the queue is empty or contains some data (buffer_contents is less than 2^n). If this is the case, the following is done:

buffer[in % (2^n)] = data 
in = (in + 1) % (2^(n+1)) 

Reading must only take place if the queue is full or if it contains valid data (buffer_contents is not 0 and is less than or equal to 2^n). To read, the following actions are performed:

data = buffer[out % (2^n)] 
out = (out + 1) % (2^(n+1)) 

How can we be sure this is safe for interprocess communication?

Writing to a queue

If the writer starts by ensuring that the queue is not full (or overrun), the queue will never overrun after the test, because you are the only one capable of filling up the queue.

If the reader can preempt the writer, there are two possible behaviours:

The reader preempts the writer before the incremented value of 'in' is written

or:

The reader preempts the writer after the incremented value of 'in' is written.

Both of these behaviours are safe (i.e. will not result in the reader attempting to read a partly written value).

Reading from a queue

If the reader starts by ensuring the queue is not empty, the queue will never underrun after the test, because the reader is the only thread capable of emptying the queue.

If the writer can preempt the reader, there are two possible behaviours:

The writer preempts the reader before the incremented value of 'out' is written

or:

The writer preempts the reader after the incremented value of 'out' is written.

Both of these behaviours are safe (i.e. will not result in the writer attempting to overwrite a partly read value). Short C implementation:

#define N 4
#define buffer_contents ((in-out)%(1<<(N+1)))

void * buffer[1<<N];
unsigned int in;
unsigned int out;

void enqueue (void * data)
{
	if (buffer_contents==(1<<N)) return; // full
	buffer[in % (1<<N)] = data;
	in = (in + 1) % (1<<(N+1));
}


void * dequeue (void)
{
	void * data;
	if (buffer_contents==0) return NULL; // empty
	data = buffer[out % (1<<N)];
	out = (out + 1) % (1<<(N+1));
	return data;
}

DO-178C webinars

DO178C webinars

White papers

Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook Efficient Verification Through the DO-178C Life Cycle
A Commercial Solution for Safety-Critical Multicore Timing Analysis
  • Solutions
    • Rapita Verification Suite
    • RapiTest
    • RapiCover
    • RapiTime
    • RapiTask
    • MACH178

    • Verification and Validation Services
    • Qualification
    • Training
    • Integration
  • Latest
  • Latest menu

    • News
    • Blog
    • Events
    • Videos
  • Downloads
  • Downloads menu

    • Brochures
    • Webinars
    • White Papers
    • Case Studies
    • Product briefs
    • Technical notes
    • Software licensing
  • Company
  • Company menu

    • About Rapita
    • Careers
    • Customers
    • Distributors
    • Industries
    • Locations
    • Partners
    • Research projects
    • Contact
  • Discover
    • Multicore Timing Analysis
    • Embedded Software Testing Tools
    • Worst Case Execution Time
    • WCET Tools
    • Code coverage for Ada, C & C++
    • MC/DC Coverage
    • Verifying additional code for DO-178C
    • Timing analysis (WCET) & Code coverage for MATLAB® Simulink®
    • Data Coupling & Control Coupling
    • Aerospace Software Testing
    • Automotive Software Testing
    • Certifying eVTOL
    • DO-178C
    • AC 20-193 and AMC 20-193
    • ISO 26262
    • What is CAST-32A?

All materials © Rapita Systems Ltd. 2025 - All rights reserved | Privacy information | Trademark notice Subscribe to our newsletter