Your browser does not support JavaScript! Skip to main content
Free 30-day trial DO-178C Handbook RapiCoupling Preview DO-178C Multicore Training Multicore Resources
Rapita Systems
 

Industry leading verification tools

Rapita Verification Suite (RVS)

RapiTest - Functional testing for critical software RapiCover - Low-overhead coverage analysis for critical software RapiTime - In-depth execution time analysis for critical software RapiTask - RTOS scheduling visualization RapiCoverZero - Zero-footprint coverage analysis RapiTimeZero - Zero-footprint timing analysis RapiTaskZero - Zero-footprint event-level scheduling analysis RVS Qualification Kits - Tool qualification for DO-178 B/C and ISO 26262 projects RapiCouplingPreview - DCCC analysis

Multicore Verification

MACH178 - Multicore Avionics Certification for High-integrity DO-178C projects MACH178 Foundations - Lay the groundwork for A(M)C 20-193 compliance Multicore Timing Solution - Solving the challenges of multicore timing analysis RapiDaemon - Analyze interference in multicore systems

Other

RTBx - The ultimate data logging solution Sim68020 - Simulation for the Motorola 68020 microprocessor

RVS Software Policy

Software licensing Product life cycle policy RVS Assurance issue policy RVS development roadmap

Industry leading verification services

Engineering Services

V&V Services Data Coupling & Control Coupling Object code verification Qualification Training Consultancy Tool Integration Support

Latest from Rapita HQ

Latest news

Rapita partners with Asterios Technologies to deliver solutions in multicore certification
SAIF Autonomy to use RVS to verify their groundbreaking AI platform
RVS 3.22 Launched
Hybrid electric pioneers, Ascendance, join Rapita Systems Trailblazer Partnership Program
View News

Latest from the Rapita blog

What does AMACC Rev B mean for multicore certification?
How emulation can reduce avionics verification costs: Sim68020
Multicore timing analysis: to instrument or not to instrument
How to certify multicore processors - what is everyone asking?
View Blog

Latest discovery pages

Military Drone Certifying Unmanned Aircraft Systems
control_tower DO-278A Guidance: Introduction to RTCA DO-278 approval
Picture of a car ISO 26262
DCCC Image Data Coupling & Control Coupling
View Discovery pages

Upcoming events

IEEE SMC-IT/SCC 2025
2025-07-28
DASC 2025
2025-09-14
DO-178C Multicore In-person Training (Fort Worth, TX)
2025-10-01
DO-178C Multicore In-person Training (Toulouse)
2025-11-04
View Events

Technical resources for industry professionals

Latest White papers

Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP
Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle
View White papers

Latest Videos

Requirements traceability with RapiTest and Polarion ALM
How to make AI safe in autonomous systems with SAIF
Rapita Systems - Safety Through Quality
Simulation for the Motorola 68020 microprocessor with Sim68020
View Videos

Latest Case studies

GMV case study front cover
GMV verify ISO26262 automotive software with RVS
Kappa: Verifying Airborne Video Systems for Air-to-Air Refueling using RVS
Supporting DanLaw with unit testing and code coverage analysis for automotive software
View Case studies

Other Resources

 Webinars

 Brochures

 Product briefs

 Technical notes

 Research projects

 Multicore resources

Discover Rapita

Who we are

The company menu

  • About us
  • Customers
  • Locations
  • Partners & Distributors
  • Research projects
  • Contact us
  • Careers
  • Working at Rapita

Industries

  Civil Aviation (DO-178C)   Automotive (ISO 26262)   Military & Defense   Space

US office

+1 248-957-9801
info@rapitasystems.com Rapita Systems, Inc., 41131 Vincenti Ct., Novi, MI 48375, USA

UK office

+44 (0)1904 413945
info@rapitasystems.com Rapita Systems Ltd., Atlas House, Osbaldwick Link Road, York, YO10 3JB, UK

Spain office

+34 93 351 02 05
info@rapitasystems.com Rapita Systems S.L., Parc UPC, Edificio K2M, c/ Jordi Girona, 1-3, Barcelona 08034, Spain
Back to Top Contact Us

Software Optimization Techniques #15: Removing Code From the Worst-Case Path

2011-05-25

Continuing the series of blog posts on optimizing embedded software with the aim of improving (i.e. reducing) worst-case execution times, this week’s topic is removing code from the worst-case path.

Software optimization techniques which improve worst-case execution times #15: Removing Code From the Worst-Case Path

A useful approach to take when attempting to minimise the worst-case execution time is to review the code on the worst-case path, asking whether all the code found on that path implements functionality that is essential or whether some of it could be carried out elsewhere.

There are two commonly used constructs that can lead to unnecessary code appearing on the worst-case path. These are if…else if…else and switch statements.

Example: if-else if-else

if(length == 0)
	{
		/* process empty message */
	}
	else if(length < 50)
	{
		/* process short message */
	}
	else if(length < 100)
	{
		/* process medium message */
	}
	else
	{
		/* process long message */
		/* worst-case path */
	}

Consider the code in the example above. Let us assume that the worst-case execution time of the code has been analysed and that the code in the final else branch, used to process long messages, is on the worst-case path. To reach the final else branch, each of the three conditions needs to be evaluated. However this is unnecessary. The code could be reordered so that the first condition evaluated is (length >= 100) as shown below. Although the re-ordered code implements exactly the same functionality, the evaluation of two conditions has been removed from the worst-case path. Note that this optimisation could be the exact opposite of optimising for best average-case behaviour; for example if empty messages are the most common.

Example: Re-ordered conditions

if(length >= 100)
	{
		/* process long message */
		/* shorter worst-case path */
	}
	else if(length >= 50)
	{
		/* process medium message */
	}
	else if(length > 0)
	{
		/* process short message */
	}
	else
	{
		/* process empty message */
	}

Switch statements are often expanded by the compiler into what is effectively a long series of if…else if…else constructs. Here, the same style of optimisation can be applied. The case branch that is on the worst-case path should be placed first in the switch statement. It is wise to check the compiler documentation or assembler code produced to determine how switch statements are implemented and to ensure that the order in which the cases are implemented is as expected.

Next week: Removing average case optimizations

DO-178C webinars

DO178C webinars

White papers


Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP
Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle

A Commercial Solution for Safety-Critical Multicore Timing Analysis

Related blog posts

Conditional code without branches

.
2015-12-10

Optimising for code size might not do what you expect - a GCC and PowerPC example

.
2015-02-09

Multi-core pitfalls: unintended code synchronization

.
2015-01-07

Is your compiler smarter than an undergraduate?

.
2013-11-13

Pagination

  • Current page 1
  • Page 2
  • Page 3
  • Page 4
  • Page 5
  • Page 6
  • Page 7
  • Next page Next ›
  • Last page Last »
  • Solutions
    • Rapita Verification Suite
    • RapiTest
    • RapiCover
    • RapiTime
    • RapiTask
    • MACH178

    • Verification and Validation Services
    • Qualification
    • Training
    • Integration
  • Latest
  • Latest menu

    • News
    • Blog
    • Events
    • Videos
  • Downloads
  • Downloads menu

    • Brochures
    • Webinars
    • White Papers
    • Case Studies
    • Product briefs
    • Technical notes
    • Software licensing
  • Company
  • Company menu

    • About Rapita
    • Careers
    • Customers
    • Distributors
    • Industries
    • Locations
    • Partners
    • Research projects
    • Contact
  • Discover
    • Multicore Timing Analysis
    • Embedded Software Testing Tools
    • Worst Case Execution Time
    • WCET Tools
    • Code coverage for Ada, C & C++
    • MC/DC Coverage
    • Verifying additional code for DO-178C
    • Timing analysis (WCET) & Code coverage for MATLAB® Simulink®
    • Data Coupling & Control Coupling
    • Aerospace Software Testing
    • DO-178C
    • Meeting DO-178C Objectives
    • AC 20-193 and AMC 20-193
    • Meeting A(M)C 20-193 Objectives
    • Certifying eVTOL
    • Certifying UAS

All materials © Rapita Systems Ltd. 2025 - All rights reserved | Privacy information | Trademark notice Subscribe to our newsletter