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Rapita Verification Suite (RVS)

RapiTest - Functional testing for critical software RapiCover - Low-overhead coverage analysis for critical software RapiTime - In-depth execution time analysis for critical software RapiTask - RTOS scheduling visualization RapiCoverZero - Zero-footprint coverage analysis RapitimeZero - Zero-footprint timing analysis RapiTaskZero - Zero-footprint event-level scheduling analysis RVS Qualification Kits - Tool qualification for DO-178 B/C and ISO 26262 projects RapiCouplingPreview - DCCC analysis

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MACH178 - Multicore Avionics Certification for High-integrity DO-178C projects MACH178 Foundations - Lay the groundwork for A(M)C 20-193 compliance Multicore Timing Solution - Solving the challenges of multicore timing analysis RapiDaemon - Analyze interference in multicore systems

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RTBx - The ultimate data logging solution Sim68020 - Simulation for the Motorola 68020 microprocessor

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Rapita partners with Asterios Technologies to deliver solutions in multicore certification
SAIF Autonomy to use RVS to verify their groundbreaking AI platform
RVS 3.22 Launched
Hybrid electric pioneers, Ascendance, join Rapita Systems Trailblazer Partnership Program
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Latest from the Rapita blog

How emulation can reduce avionics verification costs: Sim68020
Multicore timing analysis: to instrument or not to instrument
How to certify multicore processors - what is everyone asking?
Data Coupling Basics in DO-178C
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Latest discovery pages

Military Drone Certifying Unmanned Aircraft Systems
control_tower DO-278A Guidance: Introduction to RTCA DO-278 approval
Picture of a car ISO 26262
DCCC Image Data Coupling & Control Coupling
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Upcoming events

IEEE SMC-IT/SCC 2025
2025-07-28
DASC 2025
2025-09-14
DO-178C Multicore In-person Training (Fort Worth, TX)
2025-10-01
DO-178C Multicore In-person Training (Toulouse)
2025-11-04
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Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP
Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle
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How to make AI safe in autonomous systems with SAIF
Rapita Systems - Safety Through Quality
Simulation for the Motorola 68020 microprocessor with Sim68020
AI-driven Requirements Traceability for Faster Testing and Certification
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GMV case study front cover
GMV verify ISO26262 automotive software with RVS
Kappa: Verifying Airborne Video Systems for Air-to-Air Refueling using RVS
Supporting DanLaw with unit testing and code coverage analysis for automotive software
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+1 248-957-9801
info@rapitasystems.com Rapita Systems, Inc., 41131 Vincenti Ct., Novi, MI 48375, USA

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+44 (0)1904 413945
info@rapitasystems.com Rapita Systems Ltd., Atlas House, Osbaldwick Link Road, York, YO10 3JB, UK

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+34 93 351 02 05
info@rapitasystems.com Rapita Systems S.L., Parc UPC, Edificio K2M, c/ Jordi Girona, 1-3, Barcelona 08034, Spain
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ERTS Congress 2024

Event date
2024-06-11 to 2024-06-12
Event location
Toulouse
Rapita's activities
Exhibiting

ERTS Congress 2024

The  Embedded Real Time Systems (ERTS) Congress is an annual, international, cross-sector event on embedded software and systems. It serves as a platform for researchers, industry professionals, and academics to come together and discuss the latest advancements in real-time systems. The congress features presentations, workshops, and networking opportunities, making it a valuable gathering for those working in embedded software and systems seeing you there.

Rapita will be exhibiting at this year's event. We are excited to see you there!

Separation of functional and time interferences concerns for efficient AMC 20-193 compliance

  Day 1 17:00-18:00

  Lauraguais Room

  D. Chabrol, J. Guyomarc'H, F. Siron, G. Phavorin, S. Thompson, E. Jenn & F. Thurieau

Safety-critical real-time systems must comply with stringent certification requirements, including temporal ones. Failure to comply with those temporal requirements may contribute to the system failure. Therefore, timing considerations, such as response times, are of the foremost importance for such systems.

As the use of multi-/many-core hardware platforms is becoming inevitable in the avionics industry, due to the increasing computing performance required by modern embedded systems, integration activities are getting more and more complex. Increasing concurrency and parallelism exacerbates integration issues and introduces new challenging problems. 

To answer those challenges, certification authorities have issued guidelines, referenced as A(M)C 20-193, describing some objectives to fulfill for multi-/many-core integration. The present paper describes how a time-aware approach, based on the Synchronous Logical Execution Time paradigm (sLET), makes the design and integration of A(M)C 20-193 compliant safety-critical multi-/many-core systems easier by separating functional and time interferences concerns.

The paper was produced by authors:

  • Damien Chabrol - ASTERIOS Technologies, France
  • Jean Guyomarc'H - ASTERIOS Technologies, France
  • Fabien Siron - ASTERIOS Technologies, France
  • Guillaume Phavorin - ASTERIOS Technologies, France
  • Sam Thompson - Rapita Systems Ltd, United Kingdom
  • Eric Jenn - IRT Saint Exupéry, France
  • François Thurieau - Safran Electronics & Defense, France

More information about the program is available at on ERTS' website.

 

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