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Rapita Systems
 

Industry leading verification tools

Rapita Verification Suite (RVS)

RapiTest - Functional testing for critical software RapiCover - Low-overhead coverage analysis for critical software RapiTime - In-depth execution time analysis for critical software RapiTask - RTOS scheduling visualization RapiCoverZero - Zero-footprint coverage analysis RapitimeZero - Zero-footprint timing analysis RapiTaskZero - Zero-footprint event-level scheduling analysis RVS Qualification Kits - Tool qualification for DO-178 B/C and ISO 26262 projects RapiCoupling - DCCC analysis

Multicore Verification

MACH178 - Multicore Avionics Certification for High-integrity DO-178C projects MACH178 Foundations - Lay the groundwork for A(M)C 20-193 compliance Multicore Timing Solution - Solving the challenges of multicore timing analysis RapiDaemon - Analyze interference in multicore systems

Other

RTBx - The ultimate data logging solution Sim68020 - Simulation for the Motorola 68020 microprocessor

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Latest from Rapita HQ

Latest news

Rapita partners with Asterios Technologies to deliver solutions in multicore certification
SAIF Autonomy to use RVS to verify their groundbreaking AI platform
RVS 3.22 Launched
Hybrid electric pioneers, Ascendance, join Rapita Systems Trailblazer Partnership Program
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Latest from the Rapita blog

How emulation can reduce avionics verification costs: Sim68020
Multicore timing analysis: to instrument or not to instrument
How to certify multicore processors - what is everyone asking?
Data Coupling Basics in DO-178C
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Latest discovery pages

Military Drone Certifying Unmanned Aircraft Systems
control_tower DO-278A Guidance: Introduction to RTCA DO-278 approval
Picture of a car ISO 26262
DCCC Image Data Coupling & Control Coupling
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Upcoming events

IEEE SMC-IT/SCC 2025
2025-07-28
DASC 2025
2025-09-14
DO-178C Multicore In-person Training (Fort Worth, TX)
2025-10-01
DO-178C Multicore In-person Training (Toulouse)
2025-11-04
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Technical resources for industry professionals

Latest White papers

Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP
Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle
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Latest Videos

How to make AI safe in autonomous systems with SAIF
Rapita Systems - Safety Through Quality
Simulation for the Motorola 68020 microprocessor with Sim68020
AI-driven Requirements Traceability for Faster Testing and Certification
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Latest Case studies

GMV case study front cover
GMV verify ISO26262 automotive software with RVS
Kappa: Verifying Airborne Video Systems for Air-to-Air Refueling using RVS
Supporting DanLaw with unit testing and code coverage analysis for automotive software
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US office

+1 248-957-9801
info@rapitasystems.com Rapita Systems, Inc., 41131 Vincenti Ct., Novi, MI 48375, USA

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+44 (0)1904 413945
info@rapitasystems.com Rapita Systems Ltd., Atlas House, Osbaldwick Link Road, York, YO10 3JB, UK

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+34 93 351 02 05
info@rapitasystems.com Rapita Systems S.L., Parc UPC, Edificio K2M, c/ Jordi Girona, 1-3, Barcelona 08034, Spain
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Rapita Systems S.L.

Rapita Systems Spain offices

Multicore experts based in Barcelona

  •  Platform analysis
  •  RapiDaemon interference generators
ContactRead about the acquisition
  • About RSS
  • Solutions

About Rapita Systems S.L.

Rapita Systems S.L. (RSS) delivers solutions to verify and certify the software timing behavior of multicore processors in safety-critical embedded settings. This groundbreaking technology was pioneered at the BSC-CNS and is now mature and available commercially to industry via Rapita's MACH178 solution.

RSS was formed when Maspa Technologies S.L. was acquired by Danlaw Inc., Rapita Systems' parent company. Read more here.

Solutions

Solutions

As Rapita Systems' Hardware Centre of Excellence, RSS provides a range of services and tools to support multicore verification, including platform analysis, RapiDaemon interference generators and contention modeling. These solutions are used to identify and measure the impact that interference can have on multicore-hosted software applications.

The solutions provides by RSS form a cornerstone of the MACH178 and Multicore Timing solutions, which provide a pathway to certifying the next generation of multicore embedded avionics and automotive systems.

Case study: Airbus

Rapita Systems S.L., then operating as Maspa Technologies S.L., played a key role in Airbus’ successful certification of the first ever ‘fully-automatic air-to-air refueling (A3R) operation with a boom system’. Timing analysis and characterization services were provided to Airbus that were key to building a certification argument for this advanced multicore avionics system.

Airbus logo

Platform analysis

The verification of increasingly complex multicore COTS SoCs is a common challenge for embedded time-critical systems, which requires a detailed understanding of the hardware platform being used. Understanding a platform in enough depth to support verification, especially for projects undergoing DO-178C or similar certification, requires specialist knowledge.

The Rapita Systems S.L. team are world-leading specialists in understanding multicore platforms, with decades of experience in computer architecture and performance analysis. 

This gives them the expertise needed to distil platform information from extensive (often 1,000s of pages long) technical reference manuals into actionable insights that support key activities including the following: 

  • Critical Configuration Settings (CCS) Analysis
  • Interference Channel (IC) Analysis
  • Hardware Event Monitor Analysis and Validation

Solutions

RapiDaemons for analyzing timing interference

Qualifiable interference generators are at the heart of multicore timing analysis solutions. Rapita Systems S.L. (RSS) builds on long-term expertise in the design and deployment of specialized interference generators for timing analysis and identification of performance bottlenecks. Rapita Systems interference generators, developed by RSS, are sold as "RapiDaemons".

RapiDaemons are simple, well-crafted pieces of code that operate at the lowest interface between hardware and software. They are designed and refined to stress specific interference channels through applying contention on shared hardware resources.

Contention on shared hardware resources is a common source of interference in multicore platforms, as when a resource arbitrates multiple simultaneous requests, this can cause timing delays. RapiDaemons are designed to generate specific activities on specific shared resources, triggering a predefined effect on a specific interference channel with minimal impact on other interference channels. This supports the application of various verification methodologies for multicore systems.

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