Your browser does not support JavaScript! Skip to main content
Free 30-day trial DO-178C Handbook RapiCoupling Preview DO-178C Multicore Training Multicore Resources
Rapita Systems
 

Industry leading verification tools & services

Rapita Verification Suite (RVS)

  RapiTest - Unit/system testing  RapiCover - Structural coverage analysis  RapiTime - Timing analysis (inc. WCET)  RapiTask - Scheduling visualization  RapiCoverZero - Zero footprint coverage analysis  RapiTimeZero - Zero footprint timing analysis  RapiTaskZero - Zero footprint scheduling analysis  RapiCouplingPreview - DCCC analysis

Multicore Verification

  MACH178  MACH178 Foundations  Multicore Timing Solution  RapiDaemons

Engineering Services

  V&V Services  Data Coupling & Control Coupling  Object code verification  Qualification  Training  Consultancy  Tool Integration  Support

Industries

  Civil Aviation (DO-178C)   Automotive (ISO 26262)   Military & Defense   Space

Other

RTBx Mx-Suite Software licensing Product life cycle policy RVS Assurance issue policy RVS development roadmap

Latest from Rapita HQ

Latest news

SAIF Autonomy to use RVS to verify their groundbreaking AI platform
RVS 3.22 Launched
Hybrid electric pioneers, Ascendance, join Rapita Systems Trailblazer Partnership Program
Magline joins Rapita Trailblazer Partnership Program to support DO-178 Certification
View News

Latest from the Rapita blog

Multicore timing analysis: to instrument or not to instrument
How to certify multicore processors - what is everyone asking?
Data Coupling Basics in DO-178C
Control Coupling Basics in DO-178C
View Blog

Latest discovery pages

control_tower DO-278A Guidance: Introduction to RTCA DO-278 approval
Picture of a car ISO 26262
DCCC Image Data Coupling & Control Coupling
Additional Coe verification thumb Verifying additional code for DO-178C
View Discovery pages

Upcoming events

DASC 2025
2025-09-14
DO-178C Multicore In-person Training (Fort Worth, TX)
2025-10-01
DO-178C Multicore In-person Training (Toulouse)
2025-11-04
HISC 2025
2025-11-13
View Events

Technical resources for industry professionals

Latest White papers

Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP
Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle
View White papers

Latest Videos

Rapita Systems - Safety Through Quality
Simulation for the Motorola 68020 microprocessor with Sim68020
AI-driven Requirements Traceability for Faster Testing and Certification
Multicore software verification with RVS 3.22
View Videos

Latest Case studies

GMV case study front cover
GMV verify ISO26262 automotive software with RVS
Kappa: Verifying Airborne Video Systems for Air-to-Air Refueling using RVS
Supporting DanLaw with unit testing and code coverage analysis for automotive software
View Case studies

Other Resources

 Webinars

 Brochures

 Product briefs

 Technical notes

 Research projects

 Multicore resources

Discover Rapita

Who we are

The company menu

  • About us
  • Customers
  • Distributors
  • Locations
  • Partners
  • Research projects
  • Contact us

US office

+1 248-957-9801
info@rapitasystems.com
Rapita Systems, Inc.
41131 Vincenti Ct.
Novi
MI 48375
USA

UK office

+44 (0)1904 413945
info@rapitasystems.com
Rapita Systems Ltd.
Atlas House
Osbaldwick Link Road
York, YO10 3JB
UK

Spain office

+34 93 351 02 05
info@rapitasystems.com
Rapita Systems S.L.
Parc UPC, Edificio K2M
c/ Jordi Girona, 1-3
Barcelona 08034
Spain

Working at Rapita

Careers

Careers menu

  • Current opportunities & application process
  • Working at Rapita
Back to Top Contact Us

Hardware acceleration features that make real-time hard – pipelined architectures

Breadcrumb

  1. Home
2012-11-28

In a recent blog post we observed how the presence of advanced hardware features in modern processors makes it more difficult to establish the worst-case execution time (WCET) of an application. Continuing this theme, let’s examine the use of pipelined processor architectures and the effect that this has on WCET in real-time systems.

Pipelined processor architectures explained

The inclusion of a pipeline increases the instruction throughput of a processor by increasing the number of operations that the CPU can perform simultaneously. Typically, a pipelined architecture will divide each instruction into a sequence of steps, where each step can be executed in a single clock cycle. An example of this is the classic RISC pipeline, which divides the execution of an instruction into five separate stages. More modern designs use longer pipelines allowing increased maximum throughput and higher clock speeds.

How do pipelined processor architectures affect WCET in real-time systems?

Although the use of a pipeline increases the overall instruction throughput, it becomes more difficult to predict the length of time that it will take to execute a given instruction. This is particularly the case where the result of one instruction is used as a parameter to the next, as the pipeline must wait until the result is ready before it can continue processing. This is known as a stall in the pipeline.

A major cause of pipeline stalls is branches in the code, which are typically implemented as conditional jumps based on the state of a condition flag or other register value. Until the calculation of the condition is complete, the CPU is unable to fetch the next instruction, and so the pipeline stalls until the branch destination is known.

The length of the stall depends on the number of stages in the pipeline prior to the execution stage, so architectures with longer pipelines generally experience longer stall periods. In code with large numbers of branches, this can result in the pipeline being stalled for a significant proportion of the total execution time, reducing the overall throughput of the pipeline.

Overcoming pipeline stalls with branch prediction algorithms

To combat this problem, modern processors incorporate branch prediction algorithms that aim to reduce the number of pipeline stalls caused by branches. Branch prediction aims to guess the outcome of a branch instruction before it is executed, allowing the CPU to continue executing instructions in the time where it would otherwise experience a pipeline stall. The most naïve form of branch prediction assumes that all branches are always taken: statistically, this approach results in correct prediction of branches half the time. Advanced branch prediction algorithms are able to correctly predict which branch will be taken in excess of 90% of the time.

What effect does branch prediction have on WCET?

The use of branch prediction in CPUs greatly increases the total instruction throughput of the processor, but causes problems for WCET analysis. Because of the delaying effect of a pipeline stall, the execution time of a branch may be considerably longer if the branch predictor is incorrect than it would be if the correct outcome was predicted. This leads to a significant difference between average-case execution and the potential worst-case time. Assuming that the branch prediction is always incorrect for every branch will ensure that the WCET value is not optimistic, but often leads to measurements that are highly pessimistic. Static analysis techniques employ statistical methods to derive an upper bound on the number of branch predictions that will be incorrect, but this is a complex procedure that must be repeated for each analysis.

RapiTime and WCET

For measurement-based techniques, such as end-to-end it becomes increasingly important to ensure that the worst-case path through the code is adequately exercised and that the data used is sufficiently representative to expose all the possible incorrect branch predictions.

RapiTime combines the structural model of the code derived during instrumentation with the timing data it derives from the execution trace. Using this combined data, RapiTime predicts the worst-case path through the code and the worst-case execution time.

RapiTime's approach to testing and the detailed information provided in the RapiTime report can be used to ensure that testing is effective and provide assurance that the calculated WCET value is correct.

DO-178C webinars

DO178C webinars

White papers

Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook Efficient Verification Through the DO-178C Life Cycle
A Commercial Solution for Safety-Critical Multicore Timing Analysis

Related blog posts

How did the first real-time embedded system also produce the first timing bug?

.
2019-07-16

Unboxing the new RTBx

.
2017-07-25

Optimising for code size might not do what you expect - a GCC and PowerPC example

.
2015-02-09

Lesser used PowerPC instructions

.
2014-02-25

Pagination

  • Current page 1
  • Page 2
  • Page 3
  • Page 4
  • Next page Next ›
  • Last page Last »
  • Solutions
    • Rapita Verification Suite
    • RapiTest
    • RapiCover
    • RapiTime
    • RapiTask
    • MACH178

    • Verification and Validation Services
    • Qualification
    • Training
    • Integration
  • Latest
  • Latest menu

    • News
    • Blog
    • Events
    • Videos
  • Downloads
  • Downloads menu

    • Brochures
    • Webinars
    • White Papers
    • Case Studies
    • Product briefs
    • Technical notes
    • Software licensing
  • Company
  • Company menu

    • About Rapita
    • Careers
    • Customers
    • Distributors
    • Industries
    • Locations
    • Partners
    • Research projects
    • Contact
  • Discover
    • Multicore Timing Analysis
    • Embedded Software Testing Tools
    • Worst Case Execution Time
    • WCET Tools
    • Code coverage for Ada, C & C++
    • MC/DC Coverage
    • Verifying additional code for DO-178C
    • Timing analysis (WCET) & Code coverage for MATLAB® Simulink®
    • Data Coupling & Control Coupling
    • Aerospace Software Testing
    • Automotive Software Testing
    • Certifying eVTOL
    • DO-178C
    • AC 20-193 and AMC 20-193
    • ISO 26262
    • What is CAST-32A?

All materials © Rapita Systems Ltd. 2025 - All rights reserved | Privacy information | Trademark notice Subscribe to our newsletter