We work with many different embedded microcontrollers at Rapita Systems, so it’s useful to understand the need for timers and how to set up and use them. In most systems this involves interacting with several registers and some potentially confusing juggling of clock divisors and the like. However on a TriCore system there is a much easier option.
The TriCore processors have the System Timer (STM) which is a monstrous 56 bits wide. This is very nice if you need an extremely long-running high-precision timer. As one TriCore data sheet notes, this gives 28.56 years at 80MHz.
It starts automatically after reset and cannot be written to - only read from. From our perspective this is a very nice timer to use; timers which are potentially reset or modified by system code that we're not aware of can cause problems.
It's rare that we need more than a 32-bit wide timestamp for our instrumentation (especially when you consider that maximum clock frequencies we're generally encountering are about 200MHz). Using only 32 bits does mean that counter rollover can occur relatively frequently, so this does need to be handled in your code.
Let’s suppose that you want to capture the full 56 bits, without risking a rollover in-between the capture of the upper and lower words. Atomic actions won’t have any effect on timers and pausing timers to complete a read back is overkill. Thankfully Infineon have thought of this. Read a value from
STM_TIM0 (the least significant word) and the
STM_CAP register will automatically latch the upper 24 bits of the STM timer, to be read back at your leisure e.g.:
unsigned int lowerword, upper_24bits; lowerword = STM_TIM0.U // dependant on the compiler used (this is TASKING) uppert_24bits = STM_CAP.U
The default rate of the System Timer depends on the flavor of TriCore that you have. From the user manuals that I’ve seen it will either be
fSYS/2 (e.g. in TC1762) or
fFPI/2 . This divisor can be modified, which is best done in
cstart (the C start up code which executes before the main ( ) function), by setting bits 10:8 (the RMC bit-field) in the
STM_CLC register .
These bits have the following effect:
|000||No clock input|
|001||Clock at fSYS|
|010||Clock at fSYS|
|011||Clock at fSYS|
|111||Clock at fSYS|
So for example in
cstart you may have the line:
STM_CLC.U = 0x00000100; // set system clock to run at fsys/2
One philosophical point comes to mind on this: if your system experiences timer rollover once every 14 years (if running at 160MHz), the likelihood of residual timing rollover logic faults remaining in the software seems considerably higher than would be the case if rollover happened several times per hour.
Because testing the rollover logic on this device is very difficult, given that there is no way of resetting the timer, other than performing a software reset, this raises the possibility of an entire fleet of systems failing simultaneously at 14.28 years. Instead, should you consider simply using the lower 32 bits and be sure of getting the timer rollover right?