Your browser does not support JavaScript! Skip to main content
Free 30-day trial DO-178C Handbook RapiCoupling Preview DO-178C Multicore Training Multicore Resources
Rapita Systems
 

Industry leading verification tools

Rapita Verification Suite (RVS)

RapiTest - Functional testing for critical software RapiCover - Low-overhead coverage analysis for critical software RapiTime - In-depth execution time analysis for critical software RapiTask - RTOS scheduling visualization RapiCoverZero - Zero-footprint coverage analysis RapitimeZero - Zero-footprint timing analysis RapiTaskZero - Zero-footprint event-level scheduling analysis RVS Qualification Kits - Tool qualification for DO-178 B/C and ISO 26262 projects RapiCoupling - DCCC analysis

Multicore Verification

MACH178 - Multicore Avionics Certification for High-integrity DO-178C projects MACH178 Foundations - Lay the groundwork for A(M)C 20-193 compliance Multicore Timing Solution - Solving the challenges of multicore timing analysis RapiDaemon - Analyze interference in multicore systems

Other

RTBx - The ultimate data logging solution Sim68020 - Simulation for the Motorola 68020 microprocessor

RVS Software Policy

Software licensing Product life cycle policy RVS Assurance issue policy RVS development roadmap

Industry leading verification services

Engineering Services

V&V Services Data Coupling & Control Coupling Object code verification Qualification Training Consultancy Tool Integration Support

Latest from Rapita HQ

Latest news

Rapita partners with Asterios Technologies to deliver solutions in multicore certification
SAIF Autonomy to use RVS to verify their groundbreaking AI platform
RVS 3.22 Launched
Hybrid electric pioneers, Ascendance, join Rapita Systems Trailblazer Partnership Program
View News

Latest from the Rapita blog

How emulation can reduce avionics verification costs: Sim68020
Multicore timing analysis: to instrument or not to instrument
How to certify multicore processors - what is everyone asking?
Data Coupling Basics in DO-178C
View Blog

Latest discovery pages

Military Drone Certifying Unmanned Aircraft Systems
control_tower DO-278A Guidance: Introduction to RTCA DO-278 approval
Picture of a car ISO 26262
DCCC Image Data Coupling & Control Coupling
View Discovery pages

Upcoming events

IEEE SMC-IT/SCC 2025
2025-07-28
DASC 2025
2025-09-14
DO-178C Multicore In-person Training (Fort Worth, TX)
2025-10-01
DO-178C Multicore In-person Training (Toulouse)
2025-11-04
View Events

Technical resources for industry professionals

Latest White papers

Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP
Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle
View White papers

Latest Videos

How to make AI safe in autonomous systems with SAIF
Rapita Systems - Safety Through Quality
Simulation for the Motorola 68020 microprocessor with Sim68020
AI-driven Requirements Traceability for Faster Testing and Certification
View Videos

Latest Case studies

GMV case study front cover
GMV verify ISO26262 automotive software with RVS
Kappa: Verifying Airborne Video Systems for Air-to-Air Refueling using RVS
Supporting DanLaw with unit testing and code coverage analysis for automotive software
View Case studies

Other Resources

 Webinars

 Brochures

 Product briefs

 Technical notes

 Research projects

 Multicore resources

Discover Rapita

Who we are

The company menu

  • About us
  • Customers
  • Distributors
  • Locations
  • Partners
  • Research projects
  • Contact us
  • Careers
  • Working at Rapita

Industries

  Civil Aviation (DO-178C)   Automotive (ISO 26262)   Military & Defense   Space

US office

+1 248-957-9801
info@rapitasystems.com Rapita Systems, Inc., 41131 Vincenti Ct., Novi, MI 48375, USA

UK office

+44 (0)1904 413945
info@rapitasystems.com Rapita Systems Ltd., Atlas House, Osbaldwick Link Road, York, YO10 3JB, UK

Spain office

+34 93 351 02 05
info@rapitasystems.com Rapita Systems S.L., Parc UPC, Edificio K2M, c/ Jordi Girona, 1-3, Barcelona 08034, Spain
Back to Top Contact Us

Software Optimization Techniques #7: Loop Unrolling

2011-03-10

Our series of blog posts on optimizing embedded software with the aim of improving (i.e. reducing) worst-case execution times continues with loop unrolling.

Software optimization techniques which improve worst-case execution times #7: Loop Unrolling

Improvements in worst-case execution time can usually be gained by unrolling loops. Often an appropriate compiler option can be used to unroll loops, for example the gcc options –funroll-loops unrolls loops when the number of iterations is constant whilst –funroll-all-loops unrolls all loops.

Sometimes it can be worthwhile unrolling loops by hand as loop unrolling often leads to further opportunities for optimisation.

Example: Loop

Uint32
csb3(Uint32 x)
{
Uint32 set_bits = 0;
while(x)
{
if(x & 0x1) set_bits++;
x >>= 1;
}
return set_bits;
}

In the example above, the function csb3() counts the number of set bits in a 32-bit unsigned integer: x. The termination condition checks if there are any set bits left in x (non-zero value). If so, the least significant bit is checked and x shifted right, so the next most significant bit can be checked, and so on. The worst-case execution time of this implementation occurs when the value passed is 0xFFFFFFFFU. In this case, the loop iterates 32 times with 33 evaluations of the loop condition.

Partially unrolling the loop results in an execution time that may be longer in the average case, as there are fewer opportunities for an early exit, but shorter in the worst-case. In the worst-case, the revised loop iterates just 4 times with 5 evaluations of the loop termination condition.

Unrolling the loop leads directly to further optimisation: rather than include the operation x >>= 1; four times, and compare x against 0x1, the code has been modified to use one shift by 4 and constants that equate to set bits in bit positions 0 to 3. This reduces the total number of shift operations required from 32 to 8.

Example: Partially unrolled loop

Uint32
csb4(Uint32 x)
{
Uint32 set_bits = 0;
while(x)
{
if(x & 0x1) set_bits++;
if(x & 0x2) set_bits++;
if(x & 0x4) set_bits++;
if(x & 0x8) set_bits++;
x >>= 4;
}
return set_bits;
}

Together with the loop unrolling, the reduction in the number of shift operations leads to a significant reduction in the worst-case execution time for the MPC555. However, the HC12 only has operations to shift by one bit at a time and thus the “optimised” code actually ends up resulting in a longer execution time.

Function WCET (clock ticks)
  MPC555 HC12
csb3 272 1140
csb4 151 1180
Reduction in WCET 44.5% -3.55%

Next week: Look-up tables

DO-178C webinars

DO178C webinars

White papers

Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook Efficient Verification Through the DO-178C Life Cycle
A Commercial Solution for Safety-Critical Multicore Timing Analysis

Related blog posts

Three tips for successful optimization projects

.
2010-05-20

Optimization... Is it right for you?

.
2010-05-13

Pagination

  • First page « First
  • Previous page ‹ Previous
  • Page 1
  • Page 2
  • Page 3
  • Page 4
  • Page 5
  • Page 6
  • Current page 7
  • Solutions
    • Rapita Verification Suite
    • RapiTest
    • RapiCover
    • RapiTime
    • RapiTask
    • MACH178

    • Verification and Validation Services
    • Qualification
    • Training
    • Integration
  • Latest
  • Latest menu

    • News
    • Blog
    • Events
    • Videos
  • Downloads
  • Downloads menu

    • Brochures
    • Webinars
    • White Papers
    • Case Studies
    • Product briefs
    • Technical notes
    • Software licensing
  • Company
  • Company menu

    • About Rapita
    • Careers
    • Customers
    • Distributors
    • Industries
    • Locations
    • Partners
    • Research projects
    • Contact
  • Discover
    • Multicore Timing Analysis
    • Embedded Software Testing Tools
    • Worst Case Execution Time
    • WCET Tools
    • Code coverage for Ada, C & C++
    • MC/DC Coverage
    • Verifying additional code for DO-178C
    • Timing analysis (WCET) & Code coverage for MATLAB® Simulink®
    • Data Coupling & Control Coupling
    • Aerospace Software Testing
    • DO-178C
    • Meeting DO-178C Objectives
    • AC 20-193 and AMC 20-193
    • Meeting A(M)C 20-193 Objectives
    • Certifying eVTOL
    • Cerifying UAS

All materials © Rapita Systems Ltd. 2025 - All rights reserved | Privacy information | Trademark notice Subscribe to our newsletter