Multicore processor testing and validation

Last week, Rapita Systems attended the "Multi-Core Processor Test and Validation Workshop" co-hosted by the US Air Force, Army and Navy in Dayton, Ohio.

On the first morning of the 2 day event, certification authorities from the US Air Force, Army and Navy presented their interpretation of CAST-32A and how to approach the challenges of certifying multicore military applications.

During the afternoon, Rapita's CEO, Dr. Guillem Bernat, described Rapita Systems' unique commercial solution to analyzing multicore timing behavior and producing evidence for DO-178C and CAST-32A certification. His talk, which included a demo of the approach on the YOLO object recognition software (see here for an example), was extremely well received and demonstrated how closely aligned Rapita's approach to multicore timing analysis is with that suggested by military certification authorities.

Alongside Rapita's presentation on the first afternoon, some of the world's leading multicore processor vendors presented their thoughts on the challenges of complying with CAST-32A and expressed a willingness to support multicore projects by opening up some of their highly-guarded documentation. Access to this documentation will be welcomed by both the military and civilian embedded software industries as it will help support the testing and certification of multicore applications.

During the second day, global avionics suppliers Collins Aerospace and Boeing described their approaches to achieving certification of multicore systems.

 
 
 


Throughout the event, our new Multicore Timing Analysis for DO-178C White Paper received very positive feedback from attendees and contributors.

We'd like to thank the US Air Force, Army and Navy for hosting this great event and look forward to supporting our many existing and potential customers in analyzing multicore WCET behavior in both civilian and military domains.