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Rapita Verification Suite (RVS)

RapiTest - Functional testing for critical software RapiCover - Low-overhead coverage analysis for critical software RapiTime - In-depth execution time analysis for critical software RapiTask - RTOS scheduling visualization RapiCoverZero - Zero-footprint coverage analysis RapiTimeZero - Zero-footprint timing analysis RapiTaskZero - Zero-footprint event-level scheduling analysis RVS Qualification Kits - Tool qualification for DO-178 B/C and ISO 26262 projects RapiCouplingPreview - DCCC analysis

Multicore Verification

MACH178 - Multicore Avionics Certification for High-integrity DO-178C projects MACH178 Foundations - Lay the groundwork for A(M)C 20-193 compliance RapiDaemons - Analyze interference in multicore systems

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RTBx - The ultimate data logging solution Sim68020 - Simulation for the Motorola 68020 microprocessor

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RVS 3.23 Launched
Rapita System Announces New Distribution Partnership with COONTEC
Rapita partners with Asterios Technologies to deliver solutions in multicore certification
SAIF Autonomy to use RVS to verify their groundbreaking AI platform
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Latest from the Rapita blog

How to measure stack usage through stack painting with RapiTest
What does AMACC Rev B mean for multicore certification?
How emulation can reduce avionics verification costs: Sim68020
Multicore timing analysis: to instrument or not to instrument
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Latest discovery pages

Processor How to achieve multicore DO-178C certification with Rapita Systems
Plane How to achieve DO-178C certification with Rapita Systems
Military Drone Certifying Unmanned Aircraft Systems
control_tower DO-278A Guidance: Introduction to RTCA DO-278 approval
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DO-178C Multicore In-person Training (Toulouse)
2025-11-04
HISC 2025
2025-11-13
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Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP
Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle
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Certification-Ready Rust: GNAT Pro & RVS for Avionics Standards
Accelerated software verification with RVS 3.23
Getting started with RVS
Requirements traceability with RapiTest and Polarion ALM
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Latest Case studies

Case Study Front Cover
Multicore timing analysis support for ECSS-E-ST-40C R&D with MACH178
GMV case study front cover
GMV verify ISO26262 automotive software with RVS
Kappa: Verifying Airborne Video Systems for Air-to-Air Refueling using RVS
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info@rapitasystems.com Rapita Systems, Inc., 41131 Vincenti Ct., Novi, MI 48375, USA

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info@rapitasystems.com Rapita Systems Ltd., Atlas House, Osbaldwick Link Road, York, YO10 3JB, UK

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What should we really think about measuring WCET?

Following on from my last blog post grumbling about the mixing of terminologies from timing and safety domains, this post explains some of the background to WCET analysis and what RapiTime does.

  • Read more about What should we really think about measuring WCET?

Hardware acceleration features that make real-time hard – an overview

New performance-enhancing features in modern processors can mean it is harder, not easier, to establish the worst-case execution time (WCET) of an application. Why is this happening?

  • Read more about Hardware acceleration features that make real-time hard – an overview

Hardware acceleration features that make real-time hard – pipelined architectures

In a recent blog post we observed how the presence of advanced hardware features in modern processors makes it more difficult to establish the worst-case execution time (WCET) of an application. Continuing this theme, let’s examine the use of pipelined processor architectures and the effect that this has on WCET in real-time systems.

  • Read more about Hardware acceleration features that make real-time hard – pipelined architectures

Hardware acceleration features that make real-time hard - instruction caches

Continuing our series on how the presence of advanced hardware features in modern processors makes it more difficult to establish the worst-case execution time (WCET) of an application, this week we examine the issues surrounding the use of instruction caches in CPUs and the effect that this has on WCET in real-time systems.

  • Read more about Hardware acceleration features that make real-time hard - instruction caches

Tools to help real-time embedded programmers learn their trade

Over at The Engineer the debate about "should everyone be a programmer?" rages on. Here are Zoe Stephenson's thoughts.

  • Read more about Tools to help real-time embedded programmers learn their trade

Hardware acceleration features that make real-time hard - multicore

Welcome back to the series of blog posts on how the presence of advanced hardware features in modern processors makes it more difficult to establish the worst-case execution time (WCET) of an application. This week, we consider the difficulties presented by one recent development in CPU design: multicore processors.

  • Read more about Hardware acceleration features that make real-time hard - multicore

PowerPC and TriCore timing variability: which is the more predictable?

We recently tested a system with two different processors, a PowerPC and a TriCore. For anyone concerned with variability, the results make for interesting reading.

  • Read more about PowerPC and TriCore timing variability: which is the more predictable?

If RapiTime provides Ipoint coverage, why do I need RapiCover?

Users of RapiTime will probably be aware that one of the categories of information shown in a RapiTime report is "Ipoint Coverage". So, given that RapiTime supplies coverage information, why do you need RapiCover?

  • Read more about If RapiTime provides Ipoint coverage, why do I need RapiCover?

What are “co-operative” and “pre-emptive” scheduling algorithms?

Because of their complexity, most modern systems are reliant on scheduling algorithms for efficient multitasking and multiplexing. Invariably these algorithms implement compromises based on specific objectives such as meeting deadlines. This blog post looks at two tasking models which implement different compromises depending on the objectives set by the system user: these models are called “co-operative” and “pre-emptive”.

  • Read more about What are “co-operative” and “pre-emptive” scheduling algorithms?

Is Windows Safe Mode faster for code?

In a conversation with a colleague, I found myself wondering what was the impact of running code under Windows vs a "bare metal" x86 box. One of the nice things about working for a tool vendor is that you have the tools to hand to perform these kind of experiments "for fun".

  • Read more about Is Windows Safe Mode faster for code?

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