Your browser does not support JavaScript! Skip to main content
Free 30-day trial Customer portal Careers DO-178C Handbook DO-178C Multicore Training
Rapita Systems
 

Industry leading verification tools & services

Rapita Verification Suite (RVS)

  RapiTest - Unit/system testing   RapiCover - Structural coverage analysis   RapiTime - Timing analysis (inc. WCET)   RapiTask - Scheduling visualization   RapiCoverZero - Zero footprint coverage analysis   RapiTimeZero - Zero footprint timing analysis   RapiTaskZero - Zero footprint scheduling analysis

Multicore Verification

  MACH178  Multicore Timing Solution  RapiDaemons

Engineering Services

  V & V Services  Qualification  Training  Tool Integration  Support

Industries

  Aerospace (DO-178C)  Automotive (ISO 26262)  Space

Other

RTBx Mx-Suite Software licensing Product life cycle policy RVS development roadmap

Latest from Rapita HQ

Latest news

RVS 3.19 Launched
Rapita is proud to be an ISOLDE Partner
Rapita and SYSGO underline partnership
RVS 3.18 Launched
View News

Latest from the Rapita blog

Measuring response times and more with RapiTime
Why mitigating interference alone isn’t enough to verify timing performance for multicore DO-178C projects
There are how many sources of interference in a multicore system?
Supporting modern development methodologies for verification of safety-critical software
View Blog

Latest discovery pages

do178c DO-178C Guidance: Introduction to RTCA DO-178 certification
matlab_simulink MATLAB® Simulink® MCDC coverage and WCET analysis
code_coverage_ada Code coverage for Ada, C and C++
amc-20-193 AMC 20-193
View Discovery pages

Upcoming events

DASC 2023
2023-10-01
DO-178C Multicore In-person Training (Huntsville)
2023-10-03
HISC 2023
2023-10-17
NXP's MCFA 2023
2023-10-24
View Events

Technical resources for industry professionals

Latest White papers

Sysgo WP
Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle
A Commercial Solution for Safety-Critical Multicore Timing Analysis
View White papers

Latest Videos

Viewing software behavior at a glance with RVS treemaps
Using support functions with RapiTest
Thumbnail
Streamlined software verification with RVS 3.19
Challenges of certifying multicore avionics in line with A(M)C 20-193 objectives - ATW Europe 2023
View Videos

Latest Case studies

Supporting ISO 26262 ASIL D software verification for EasyMile
RapiCover’s advanced features accelerate the certification of military UAV Engine Control
Front cover of whitepaper collins
Delivering world-class tool support to Collins Aerospace
View Case studies

Other Downloads

 Webinars

 Brochures

 Product briefs

 Technical notes

 Research projects

Discover Rapita

Who we are

The company menu

  • About us
  • Customers
  • Distributors
  • Locations
  • Partners
  • Research projects
  • Contact us

US office

+1 248-957-9801
info@rapitasystems.com
Rapita Systems, Inc.
41131 Vincenti Ct.
Novi
MI 48375
USA

UK office

+44 (0)1904 413945
info@rapitasystems.com
Rapita Systems Ltd.
Atlas House
Osbaldwick Link Road
York, YO10 3JB
UK

Spain office

+34 93 351 02 05
info@rapitasystems.com
Rapita Systems S.L.
Parc UPC, Edificio K2M
c/ Jordi Girona, 1-3
Barcelona 08034
Spain

Working at Rapita

Careers

Careers menu

  • Current opportunities & application process
  • Working at Rapita
Back to Top

What’s the difference between a SIL and a DAL? How does it affect my Code Coverage?

Breadcrumb

  1. Home
  2. Blog
  3. What’s the difference between a SIL and a DAL? How does it affect my Code Coverage?
2014-10-07

In this article I look at the different integrity levels for the DO-178C "Software Considerations in Airborne Systems and Equipment Certification" development guidance and ISO26262 "Road vehicles – Functional safety" standard, what they mean for code coverage and why they are not equivalent.

How do I find my Integrity Level?

Most safety standards use the concept of an integrity level, which is assigned to a system or a function. This level will be based on an initial analysis of the consequences of your software going wrong. Both standards have clear guidance on how to identify your integrity level. For example, DO-178C has Software Levels, which are assigned based on the outcome of "anomalous behaviour" of a software component – Level A for "Catastrophic Outcome", Level E for "No Safety Effect". ISO26262 has ASIL (Automotive Safety Integrity Level), based on the exposure to issues affecting the controllability of the vehicle. ASILs range from D for the highest severity/most probable exposure, and A as the least. So the underlying concept is similar – find out how severe the effect and how likely it is your software can go wrong. The difference is in the scales and criteria used.

Safety standard integrity levels

What does my integrity level mean?

The allocated integrity level is linked to a set of processes to follow when developing your system – the higher the level then the more rigorous and stringent these processes are. Let’s take code coverage requirements as an example. The purpose of code coverage testing is to determine how much of your code has been exercised by your requirements based test cases. It can be a powerful tool in locating any code that doesn’t trace to a requirement, or limitations in your testing. The more severe the consequences of your code going wrong, then the more evidence we need that the test cases can find potential problems in the code.

Table 1 shows the code coverage requirements for DO178C from Annex A, Table A-7 of the standard. At Level C you only need to demonstrate that your tests cover all the statements in your software. However, at Level A you need three types of code coverage, including the most stringent, Multiple Condition/Decision Coverage for which every possible condition must be shown to independently affect the decision/software’s outcome. Further, you need to run these tests and demonstrate that the testing process has been performed by someone not directly involved with the development process.

  MC/DC Decision Coverage Statement Coverage
Level A With Independence With Independence With Independence
Level B - With Independence With Independence
Level C - - Required
Level D - - -
Level E - - -

Table 1 Code Coverage Requirements in DO-178C

Compare this with the code coverage requirements in ISO26262. Table 2 shows the requirements from Tables 12 and 15 of Part 6 of ISO26262. There are two different sets, one at the unit level and one at the architectural level. Techniques are highly recommended (++) or recommended (+). No requirement for independence is there. So whilst at the highest ASIL we still require MC/DC, the requirement for how that’s achieved is different. Also code coverage must be applied at multiple abstraction levels.

  MC/DC (Unit Level) Branch Coverage (Unit Level) Statement Coverage (Unit Level) Function Coverage (Architectural Level) Call Coverage (Architectural Level)
ASIL D ++ ++ + ++ ++
ASIL C + ++ + ++ ++
ASIL B + ++ ++ + +
ASIL A + + ++ + +

Table 2 Code Coverage Requirements in ISO26262

What’s the conclusion?

The integrity level concept is in almost all safety standards in one form or another. You will need to identify your integrity level in order to understand how to satisfy the standards development requirements, and, ultimately, the body approving whether your software is acceptably safe. However, the details mean that we can’t directly compare integrity levels between standards, and the requirements may be subtly different.

DO-178C webinars

DO178C webinars

White papers

Sysgo WP Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook Efficient Verification Through the DO-178C Life Cycle
A Commercial Solution for Safety-Critical Multicore Timing Analysis
Compliance with the Future Airborne Capability Environment (FACE) standard

Related blog posts

DO-178C - Stage of Involvement 4

.
2022-04-06

DO-178C - Stage of Involvement 3

.
2022-03-23

DO-178C - Stage of Involvement 2

.
2022-03-09

DO-178C - Stage of Involvement 1

.
2022-03-01

Pagination

  • Current page 1
  • Page 2
  • Page 3
  • Page 4
  • Page 5
  • Next page Next ›
  • Last page Last »
  • Solutions
    • Rapita Verification Suite
    • RapiTest
    • RapiCover
    • RapiTime
    • RapiTask
    • MACH178

    • Verification and Validation Services
    • Qualification
    • Training
    • Integration
  • Latest
  • Latest menu

    • News
    • Blog
    • Events
    • Videos
  • Downloads
  • Downloads menu

    • Brochures
    • Webinars
    • White Papers
    • Case Studies
    • Product briefs
    • Technical notes
    • Software licensing
  • Company
  • Company menu

    • About Rapita
    • Careers
    • Customers
    • Distributors
    • Industries
    • Locations
    • Partners
    • Research projects
    • Contact
  • Discover
    • AMC 20-193
    • What is CAST-32A?
    • Multicore Timing Analysis
    • MC/DC Coverage
    • Code coverage for Ada, C & C++
    • Embedded Software Testing Tools
    • Aerospace Software Testing
    • Automotive Software Testing
    • Certifying eVTOL
    • DO-178C
    • WCET Tools
    • Worst Case Execution Time
    • Timing analysis (WCET) & Code coverage for MATLAB® Simulink®

All materials © Rapita Systems Ltd. 2023 - All rights reserved | Privacy information | Trademark notice Subscribe to our newsletter