Current opportunities at Rapita
CAST-32A Compliance Update
New paper: Surrogate Applications for Multicore Contention Modeling
Rapita hosts SCADE webinar with ANSYS
Software verification on the Solar Orbiter
Metrowerks CodeTest - How and why to upgrade
Leveraging FACE Conformance Artifacts to Support Airworthiness
Assured Multicore Partitioning for FACE Systems
DO-178C
MATLAB Simulink MCDC coverage and WCET analysis
Code coverage for Ada, C and C++
AMC 20-193
How to verify multicore hardware & software for avionics
FACE Technical Interchange Meeting
Aerospace TechWeek 2021
Safe Use of Multi-Core Processors Seminar
Solving the challenges of multicore certification
A complete solution
Having learned a lot from our active CAST-32A Compliance projects, we have been developing new products and services that support the CAST-32A compliance workflow.
Reports
Reports detailing the interference channels on a multicore platform and the results of experiments in which the impact of interference on those channels is characterized are one of the main outputs of a CAST-32A compliance project. We provide these reports for a range of multicore platforms.
Template compliance documents
For CAST-32A compliance, the compliance workflow and verification results must be detailed in DO-178C planning and results documents.
Our template CAST-32A compliance documents offer a convenient blueprint that can be used to generate final DO-178C compliance documents. These documents can be completed as part of our Platform Analysis and Characterization and Software Analysis and Characterization Services, or if you are performing the analysis yourself, you can use the templates as a starting point to writing your compliance documents.
Process documents
DO-178C certification requires detailed processes to be developed and followed for each stage of the overall DO-178C process.
We have been developing process documents that describe how to perform multicore platform and software analysis and characterization using the Rapita CAST-32A Compliance workflow. As well as providing supplementary evidence to support DO-178C certification, these documents can be used to perform this analysis and characterization yourselves.
Characterization tests
CAST-32A compliance requires evidence that worst-case execution time (WCET) analysis has taken into account interference effects on a multicore platform. WCET analysis can be supported by tests to characterize the impact of interference on the platform.
Our characterization tests include test artifacts needed to analyze the potential impact of interference on multicore platforms and perform WCET analysis of software hosted on those platforms. Characterization Tests are developed for execution using RVS and RapiDaemons.
RapiDaemon qualification
RapiDaemons, which apply configurable degrees of contention on shared multicore resources, are a key component of the CAST-32A Compliance Solution. As software tools, their use in DO-178C projects must be supported by DO-330 tool qualification evidence.
We have begun developing DO-330 qualification kits and a qualification service for RapiDaemons, which can be used to generate this evidence.
Tool automation
We have been working on new features for the Rapita Verification Suite (RVS) to better support efficient multicore timing analysis for CAST-32A compliance. These new features will be available in the upcoming RVS 3.15 release.
Merge timing results
For multicore timing analysis, large amounts of data must be collected from multiple test runs and then processed to provide CAST-32A compliance evidence. To make the analysis more efficient, data may be collected from multiple platforms or at different time points.
We have added support for these use cases to RapiTime, which now lets you merge timing data from multiple test runs into a single report for further processing.
This feature will be available in RVS 3.15.
Custom exports
Testing scenarios for multicore timing analysis typically require the collection of values of various performance monitoring counters during execution. The counters that must be collected can vary between different test runs.
We have added a feature to RVS to let you generate custom exports that include only the results you need to satisfy your test scenario. To create custom exports, you generate a template file in which you can add text, link to your requirements and test plans, and include RVS results through an API. You can then generate a report containing only the results you need each time you run your tests.
This feature will be available in RVS 3.15.
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Compatibility
We can analyze almost all multicore hardware architectures. See below for a list of systems we have analyzed.
Architectures
Here are some of the architectures we have worked with:
| SoC | Cores |
|---|---|
|
Infineon AURIX |
Tricore |
|
Nvidia Xavier |
Carmel Armv8 |
|
NXP LS1048A |
Arm A53 |
|
NXP LS1088M |
Arm A53 |
|
NXP P2041 |
PowerPC e500mc |
|
NXP T1040 |
PowerPC e5500 |
|
NXP T2080/1 |
PowerPC e6500 |
|
TI Keystone K2L |
Arm A15 |
|
Xilinx Ultrascale+ XCZU9EG |
Arm A53, Arm R5 |
RTOSs
Here are some of the RTOSs we have worked with:
| RTOS |
|---|
|
Bare metal |
|
Blackberry QNX |
|
DDC-I Deos |
|
Green Hills® INTEGRITY® |
|
Lynx Software Technologies LynxSecure |
|
SYSGO PikeOS |
|
Vector MICROSAR |
|
Wind River Helix®/VxWorks® |
